378 lines
17 KiB
LLVM
378 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GCN,SDAG,GCN-FAKE16,SDAG-FAKE16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GCN,GISEL,GCN-FAKE16,GISEL-FAKE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GCN,SDAG,GCN-REAL16,SDAG-REAL16 %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GCN,GISEL,GCN-REAL16,GISEL-REAL16 %s
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define amdgpu_ps float @global_load_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b32_idxprom:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom
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%ret = load float, ptr addrspace(1) %arrayidx, align 4
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ret float %ret
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}
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define amdgpu_ps float @global_load_b32_idx32(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b32_idx32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i32 %idx
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%ret = load float, ptr addrspace(1) %arrayidx, align 4
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ret float %ret
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}
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define amdgpu_ps float @global_load_b32_idxprom_wrong_stride(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b32_idxprom_wrong_stride:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 3, s[0:1]
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom
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%ret = load float, ptr addrspace(1) %arrayidx, align 4
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ret float %ret
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}
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define amdgpu_ps float @global_load_b16_idxprom_ioffset(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b16_idxprom_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_u16 v0, v0, s[0:1] offset:32 scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxadd
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%ld = load i16, ptr addrspace(1) %arrayidx, align 2
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%ret.i32 = zext i16 %ld to i32
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%ret = bitcast i32 %ret.i32 to float
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ret float %ret
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}
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define amdgpu_ps <2 x float> @global_load_b64_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b64_idxprom:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b64 v[0:1], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom
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%ret = load <2 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <2 x float> %ret
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}
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define amdgpu_ps <3 x float> @global_load_b96_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b96_idxprom:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxprom
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%ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <3 x float> %ret
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}
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define amdgpu_ps <3 x float> @global_load_b96_idxpromi_ioffset(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b96_idxpromi_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:192 scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxadd
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%ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <3 x float> %ret
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}
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define amdgpu_ps <4 x float> @global_load_b128_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_load_b128_idxprom:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b128 v[0:3], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(1) %p, i64 %idxprom
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%ret = load <4 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <4 x float> %ret
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}
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define amdgpu_ps float @global_load_b32_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b32_idxprom_range:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom
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%ret = load float, ptr addrspace(1) %arrayidx, align 4
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ret float %ret
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}
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define amdgpu_ps float @global_load_b32_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b32_idxprom_range_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b32 v0, v0, s[0:1] offset:64 scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxadd
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%ret = load float, ptr addrspace(1) %arrayidx, align 4
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ret float %ret
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}
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; Note: this is a byte load, there is nothing to scale
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define amdgpu_ps float @global_load_b8_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b8_idxprom_range_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_u8 v0, v0, s[0:1] offset:16
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds i8, ptr addrspace(1) %p, i64 %idxadd
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%ld = load i8, ptr addrspace(1) %arrayidx
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%ret.i32 = zext i8 %ld to i32
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%ret = bitcast i32 %ret.i32 to float
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ret float %ret
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}
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define amdgpu_ps float @global_load_b16_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b16_idxprom_range:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_u16 v0, v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxprom
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%ld = load i16, ptr addrspace(1) %arrayidx, align 2
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%ret.i32 = zext i16 %ld to i32
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%ret = bitcast i32 %ret.i32 to float
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ret float %ret
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}
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define amdgpu_ps float @global_load_b16_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b16_idxprom_range_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_u16 v0, v0, s[0:1] offset:32 scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxadd
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%ld = load i16, ptr addrspace(1) %arrayidx, align 2
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%ret.i32 = zext i16 %ld to i32
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%ret = bitcast i32 %ret.i32 to float
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ret float %ret
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}
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define amdgpu_ps <2 x float> @global_load_b64_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b64_idxprom_range:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b64 v[0:1], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom
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%ret = load <2 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <2 x float> %ret
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}
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define amdgpu_ps <3 x float> @global_load_b96_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b96_idxprom_range:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxprom
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%ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <3 x float> %ret
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}
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define amdgpu_ps <3 x float> @global_load_b96_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b96_idxprom_range_ioffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:192 scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%idxadd = add i64 %idxprom, 16
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%arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxadd
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%ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <3 x float> %ret
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}
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define amdgpu_ps <4 x float> @global_load_b128_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {
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; GCN-LABEL: global_load_b128_idxprom_range:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_load_b32 v0, v[0:1], off
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: global_load_b128 v[0:3], v0, s[0:1] scale_offset
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%idx = load i32, ptr addrspace(1) %pp, align 4, !range !0
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(1) %p, i64 %idxprom
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%ret = load <4 x float>, ptr addrspace(1) %arrayidx, align 4
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ret <4 x float> %ret
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}
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define amdgpu_ps void @global_store_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
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; GCN-LABEL: global_store_b32_idxprom:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: v_mov_b32_e32 v1, 1.0
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; GCN-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset
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; GCN-NEXT: s_endpgm
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entry:
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom
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store float 1.0, ptr addrspace(1) %arrayidx, align 4
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ret void
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}
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define amdgpu_ps void @global_store_b16_idxprom(ptr addrspace(1) align 2 inreg %p, i32 %idx) {
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; GCN-FAKE16-LABEL: global_store_b16_idxprom:
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; GCN-FAKE16: ; %bb.0: ; %entry
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; GCN-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-FAKE16-NEXT: v_mov_b32_e32 v1, 1
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|
; GCN-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset
|
|
; GCN-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GCN-REAL16-LABEL: global_store_b16_idxprom:
|
|
; GCN-REAL16: ; %bb.0: ; %entry
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|
; GCN-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GCN-REAL16-NEXT: v_mov_b16_e32 v1.l, 1
|
|
; GCN-REAL16-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset
|
|
; GCN-REAL16-NEXT: s_endpgm
|
|
entry:
|
|
%idxprom = sext i32 %idx to i64
|
|
%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxprom
|
|
store i16 1, ptr addrspace(1) %arrayidx, align 2
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @global_store_b64_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
|
|
; GCN-LABEL: global_store_b64_idxprom:
|
|
; GCN: ; %bb.0: ; %entry
|
|
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GCN-NEXT: v_mov_b64_e32 v[2:3], 1.0
|
|
; GCN-NEXT: global_store_b64 v0, v[2:3], s[0:1] scale_offset
|
|
; GCN-NEXT: s_endpgm
|
|
entry:
|
|
%idxprom = sext i32 %idx to i64
|
|
%arrayidx = getelementptr inbounds double, ptr addrspace(1) %p, i64 %idxprom
|
|
store double 1.0, ptr addrspace(1) %arrayidx, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @global_atomicrmw_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {
|
|
; GCN-LABEL: global_atomicrmw_b32_idxprom:
|
|
; GCN: ; %bb.0: ; %entry
|
|
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 1
|
|
; GCN-NEXT: global_atomic_add_u32 v0, v1, s[0:1] scale_offset scope:SCOPE_SYS
|
|
; GCN-NEXT: s_endpgm
|
|
entry:
|
|
%idxprom = sext i32 %idx to i64
|
|
%arrayidx = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %idxprom
|
|
atomicrmw add ptr addrspace(1) %arrayidx, i32 1 monotonic
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps <2 x float> @global_atomicrmw_b64_rtn_idxprom(ptr addrspace(1) align 8 inreg %p, i32 %idx) {
|
|
; GCN-LABEL: global_atomicrmw_b64_rtn_idxprom:
|
|
; GCN: ; %bb.0: ; %entry
|
|
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GCN-NEXT: v_mov_b64_e32 v[2:3], 1
|
|
; GCN-NEXT: global_atomic_add_u64 v[0:1], v0, v[2:3], s[0:1] scale_offset th:TH_ATOMIC_RETURN scope:SCOPE_SYS
|
|
; GCN-NEXT: s_wait_loadcnt 0x0
|
|
; GCN-NEXT: ; return to shader part epilog
|
|
entry:
|
|
%idxprom = sext i32 %idx to i64
|
|
%arrayidx = getelementptr inbounds i64, ptr addrspace(1) %p, i64 %idxprom
|
|
%ret = atomicrmw add ptr addrspace(1) %arrayidx, i64 1 monotonic
|
|
%ret.cast = bitcast i64 %ret to <2 x float>
|
|
ret <2 x float> %ret.cast
|
|
}
|
|
|
|
!0 = !{i32 0, i32 1024}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; GISEL: {{.*}}
|
|
; GISEL-FAKE16: {{.*}}
|
|
; GISEL-REAL16: {{.*}}
|
|
; SDAG: {{.*}}
|
|
; SDAG-FAKE16: {{.*}}
|
|
; SDAG-REAL16: {{.*}}
|