c245d764b8
Do not remove IMPLICIT_DEF of a physreg unless all uses have an undef flag added. Previously, only the first use instruction had undef flags added. This will cause a failure in machine instruction verification. Multi-instruction uses tested in AMDGPU/multi-use-implicit-def.mir and X86/multi-use-implicit-def.mir. --------- Signed-off-by: John Lu <John.Lu@amd.com>
50 lines
1.6 KiB
YAML
50 lines
1.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# Ensure processing an IMPLICIT_DEF of a physreg updates all uses
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# before removing the IMPLICIT_DEF. -verify-machineinstrs will
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# fail otherwise.
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# RUN: llc -mtriple=amdgcn -mcpu=gfx802 -run-pass processimpdefs -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: implicit_def_multiple_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: implicit_def_multiple_use
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; CHECK: $vgpr1_lo16 = COPY undef $vgpr0_hi16
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; CHECK-NEXT: $vgpr1_hi16 = COPY undef $vgpr0_lo16
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr0 = IMPLICIT_DEF
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$vgpr1_lo16 = COPY $vgpr0_hi16
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$vgpr1_hi16 = COPY $vgpr0_lo16
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S_ENDPGM 0
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...
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# IMPLICIT_DEF processing Will not search across basic-blocks for uses. IMPLICIT_DEF must not be deleted.
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---
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name: implicit_def_cannot_find_all_uses
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: implicit_def_cannot_find_all_uses
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF
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; CHECK-NEXT: $vgpr1_lo16 = COPY undef $vgpr0_hi16
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; CHECK-NEXT: $vgpr1_hi16 = COPY undef $vgpr0_lo16
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; CHECK-NEXT: $scc = IMPLICIT_DEF
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.0, implicit undef $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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bb.0:
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$vgpr0 = IMPLICIT_DEF
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$vgpr1_lo16 = COPY $vgpr0_hi16
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$vgpr1_hi16 = COPY $vgpr0_lo16
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$scc = IMPLICIT_DEF
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S_CBRANCH_SCC1 %bb.0, implicit $scc
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bb.1:
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...
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