431 lines
16 KiB
LLVM
431 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
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; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
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define amdgpu_kernel void @infinite_loop(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 vcc, exec, -1
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; SI-NEXT: .LBB0_1: ; %loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccnz .LBB0_1
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; SI-NEXT: ; %bb.2: ; %DummyReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop(
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; IR-NEXT: entry:
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; IR-NEXT: br label [[LOOP:%.*]]
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; IR: loop:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[LOOP]], label [[DUMMYRETURNBLOCK:%.*]]
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; IR: DummyReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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br label %loop
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}
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define amdgpu_kernel void @infinite_loop_callbr(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop_callbr:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: ;;#ASMSTART
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; SI-NEXT: ;;#ASMEND
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_callbr(
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; IR-NEXT: entry:
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; IR-NEXT: callbr void asm "", ""()
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; IR-NEXT: to label [[LOOP:%.*]] []
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; IR: loop:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[DUMMYRETURNBLOCK:%.*]]
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; IR: TransitionBlock:
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; IR-NEXT: callbr void asm "", ""()
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; IR-NEXT: to label [[LOOP]] []
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; IR: DummyReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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callbr void asm "", ""() to label %loop []
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loop:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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callbr void asm "", ""() to label %loop []
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}
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define amdgpu_kernel void @infinite_loop_ret(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop_ret:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc
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; SI-NEXT: s_cbranch_execz .LBB2_3
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; SI-NEXT: ; %bb.1: ; %loop.preheader
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 vcc, exec, -1
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; SI-NEXT: .LBB2_2: ; %loop
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccnz .LBB2_2
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; SI-NEXT: .LBB2_3: ; %UnifiedReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_ret(
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; IR-NEXT: entry:
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; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
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; IR-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
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; IR: loop:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[LOOP]], label [[UNIFIEDRETURNBLOCK]]
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; IR: UnifiedReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond = icmp eq i32 %tmp, 1
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br i1 %cond, label %loop, label %return
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loop:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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br label %loop
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return:
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ret void
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}
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define amdgpu_kernel void @infinite_loop_ret_callbr(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop_ret_callbr:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; SI-NEXT: ;;#ASMSTART
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; SI-NEXT: ;;#ASMEND
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; SI-NEXT: ; %bb.1: ; %loop.preheader
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: .LBB3_2: ; Inline asm indirect target
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; SI-NEXT: ; %UnifiedReturnBlock
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; SI-NEXT: ; Label of block must be emitted
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_ret_callbr(
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; IR-NEXT: entry:
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; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
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; IR-NEXT: [[COND32:%.*]] = zext i1 [[COND]] to i32
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; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND32]])
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; IR-NEXT: to label [[LOOP:%.*]] [label %UnifiedReturnBlock]
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; IR: loop:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
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; IR: TransitionBlock:
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; IR-NEXT: callbr void asm "", ""()
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; IR-NEXT: to label [[LOOP]] []
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; IR: UnifiedReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond = icmp eq i32 %tmp, 1
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%cond32 = zext i1 %cond to i32
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callbr void asm "", "r,!i"(i32 %cond32) to label %loop [label %return]
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loop:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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callbr void asm "", ""() to label %loop []
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return:
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ret void
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}
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define amdgpu_kernel void @infinite_loops(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loops:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b64 s[2:3], -1
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; SI-NEXT: s_cbranch_scc1 .LBB4_4
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; SI-NEXT: ; %bb.1:
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x378
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; SI-NEXT: s_and_b64 vcc, exec, -1
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; SI-NEXT: .LBB4_2: ; %loop2
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccnz .LBB4_2
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; SI-NEXT: ; %bb.3: ; %Flow
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: .LBB4_4: ; %Flow2
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; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccz .LBB4_7
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; SI-NEXT: ; %bb.5:
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt expcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 vcc, exec, 0
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; SI-NEXT: .LBB4_6: ; %loop1
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; SI-NEXT: ; =>This Inner Loop Header: Depth=1
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_mov_b64 vcc, vcc
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; SI-NEXT: s_cbranch_vccz .LBB4_6
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; SI-NEXT: .LBB4_7: ; %DummyReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loops(
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; IR-NEXT: entry:
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; IR-NEXT: br i1 poison, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
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; IR: loop1:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[LOOP1]], label [[DUMMYRETURNBLOCK:%.*]]
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; IR: loop2:
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; IR-NEXT: store volatile i32 888, ptr addrspace(1) [[OUT]], align 4
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; IR-NEXT: br i1 true, label [[LOOP2]], label [[DUMMYRETURNBLOCK]]
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; IR: DummyReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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br i1 poison, label %loop1, label %loop2
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loop1:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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br label %loop1
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loop2:
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store volatile i32 888, ptr addrspace(1) %out, align 4
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br label %loop2
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}
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define amdgpu_kernel void @infinite_loops_callbr(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loops_callbr:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: ;;#ASMSTART
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; SI-NEXT: ;;#ASMEND
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; SI-NEXT: ; %bb.1: ; %loop1
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_endpgm
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; SI-NEXT: .LBB5_2: ; Inline asm indirect target
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; SI-NEXT: ; %loop2.preheader
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; SI-NEXT: ; Label of block must be emitted
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x378
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loops_callbr(
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; IR-NEXT: entry:
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; IR-NEXT: callbr void asm "", "r,!i"(i32 poison)
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; IR-NEXT: to label [[LOOP1:%.*]] [label %loop2]
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; IR: loop1:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[DUMMYRETURNBLOCK:%.*]]
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; IR: TransitionBlock:
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; IR-NEXT: callbr void asm "", ""()
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; IR-NEXT: to label [[LOOP1]] []
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; IR: loop2:
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; IR-NEXT: store volatile i32 888, ptr addrspace(1) [[OUT]], align 4
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK1:%.*]], label [[DUMMYRETURNBLOCK]]
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; IR: TransitionBlock1:
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; IR-NEXT: callbr void asm "", ""()
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; IR-NEXT: to label [[LOOP2:%.*]] []
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; IR: DummyReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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callbr void asm "", "r,!i"(i32 poison) to label %loop1 [label %loop2]
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loop1:
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store volatile i32 999, ptr addrspace(1) %out, align 4
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callbr void asm "", ""() to label %loop1 []
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loop2:
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store volatile i32 888, ptr addrspace(1) %out, align 4
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callbr void asm "", ""() to label %loop2 []
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}
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define amdgpu_kernel void @infinite_loop_nest_ret(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop_nest_ret:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
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; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc
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; SI-NEXT: s_cbranch_execz .LBB6_5
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; SI-NEXT: ; %bb.1: ; %outer_loop.preheader
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; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
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; SI-NEXT: v_cmp_ne_u32_e64 s[0:1], 3, v0
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: .LBB6_2: ; %outer_loop
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; SI-NEXT: ; =>This Loop Header: Depth=1
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; SI-NEXT: ; Child Loop BB6_3 Depth 2
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; SI-NEXT: s_mov_b64 s[2:3], 0
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; SI-NEXT: .LBB6_3: ; %inner_loop
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; SI-NEXT: ; Parent Loop BB6_2 Depth=1
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; SI-NEXT: ; => This Inner Loop Header: Depth=2
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; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1]
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; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
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; SI-NEXT: s_cbranch_execnz .LBB6_3
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; SI-NEXT: ; %bb.4: ; %loop.exit.guard
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; SI-NEXT: ; in Loop: Header=BB6_2 Depth=1
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; SI-NEXT: s_or_b64 exec, exec, s[2:3]
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; SI-NEXT: s_mov_b64 vcc, 0
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; SI-NEXT: s_branch .LBB6_2
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; SI-NEXT: .LBB6_5: ; %UnifiedReturnBlock
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; SI-NEXT: s_endpgm
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; IR-LABEL: @infinite_loop_nest_ret(
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; IR-NEXT: entry:
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; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; IR-NEXT: [[COND1:%.*]] = icmp ne i32 [[TMP]], 1
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; IR-NEXT: br i1 [[COND1]], label [[OUTER_LOOP:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
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; IR: outer_loop:
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; IR-NEXT: br label [[INNER_LOOP:%.*]]
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; IR: inner_loop:
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; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
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; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
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; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK]]
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; IR: TransitionBlock:
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; IR-NEXT: br i1 [[COND3]], label [[INNER_LOOP]], label [[OUTER_LOOP]]
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; IR: UnifiedReturnBlock:
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; IR-NEXT: ret void
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;
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%cond1 = icmp ne i32 %tmp, 1 ; avoid following BB optimizing away through the domination
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br i1 %cond1, label %outer_loop, label %return
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outer_loop:
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; %cond2 = icmp eq i32 %tmp, 2
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; br i1 %cond2, label %outer_loop, label %inner_loop
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br label %inner_loop
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inner_loop: ; preds = %LeafBlock, %LeafBlock1
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store volatile i32 999, ptr addrspace(1) %out, align 4
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%cond3 = icmp eq i32 %tmp, 3
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br i1 %cond3, label %inner_loop, label %outer_loop
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return:
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ret void
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}
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define amdgpu_kernel void @infinite_loop_nest_ret_callbr(ptr addrspace(1) %out) {
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; SI-LABEL: infinite_loop_nest_ret_callbr:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
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; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; SI-NEXT: ;;#ASMSTART
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; SI-NEXT: ;;#ASMEND
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; SI-NEXT: ; %bb.1: ; %outer_loop.preheader
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; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
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; SI-NEXT: s_and_b64 s[0:1], exec, 0
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; SI-NEXT: s_branch .LBB7_3
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; SI-NEXT: .LBB7_2: ; %loop.exit.guard
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; SI-NEXT: ; in Loop: Header=BB7_3 Depth=1
|
|
; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
|
|
; SI-NEXT: s_cbranch_vccnz .LBB7_5
|
|
; SI-NEXT: .LBB7_3: ; %outer_loop
|
|
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; SI-NEXT: ;;#ASMSTART
|
|
; SI-NEXT: ;;#ASMEND
|
|
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_mov_b64 s[2:3], -1
|
|
; SI-NEXT: s_mov_b64 vcc, s[0:1]
|
|
; SI-NEXT: s_cbranch_vccz .LBB7_2
|
|
; SI-NEXT: ; %bb.4: ; %TransitionBlock.target.outer_loop
|
|
; SI-NEXT: ; in Loop: Header=BB7_3 Depth=1
|
|
; SI-NEXT: s_mov_b64 s[2:3], 0
|
|
; SI-NEXT: s_branch .LBB7_2
|
|
; SI-NEXT: .LBB7_5: ; Inline asm indirect target
|
|
; SI-NEXT: ; %UnifiedReturnBlock
|
|
; SI-NEXT: ; Label of block must be emitted
|
|
; SI-NEXT: s_endpgm
|
|
; IR-LABEL: @infinite_loop_nest_ret_callbr(
|
|
; IR-NEXT: entry:
|
|
; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
; IR-NEXT: [[COND1:%.*]] = icmp ne i32 [[TMP]], 1
|
|
; IR-NEXT: [[COND1_32:%.*]] = zext i1 [[COND1]] to i32
|
|
; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND1_32]])
|
|
; IR-NEXT: to label [[OUTER_LOOP:%.*]] [label %UnifiedReturnBlock]
|
|
; IR: outer_loop:
|
|
; IR-NEXT: callbr void asm "", ""()
|
|
; IR-NEXT: to label [[INNER_LOOP:%.*]] []
|
|
; IR: inner_loop:
|
|
; IR-NEXT: store volatile i32 999, ptr addrspace(1) [[OUT:%.*]], align 4
|
|
; IR-NEXT: [[COND3:%.*]] = icmp eq i32 [[TMP]], 3
|
|
; IR-NEXT: [[COND3_32:%.*]] = zext i1 [[COND3]] to i32
|
|
; IR-NEXT: br i1 true, label [[TRANSITIONBLOCK:%.*]], label [[UNIFIEDRETURNBLOCK:%.*]]
|
|
; IR: TransitionBlock:
|
|
; IR-NEXT: callbr void asm "", "r,!i"(i32 [[COND3_32]])
|
|
; IR-NEXT: to label [[INNER_LOOP]] [label %outer_loop]
|
|
; IR: UnifiedReturnBlock:
|
|
; IR-NEXT: ret void
|
|
;
|
|
entry:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%cond1 = icmp ne i32 %tmp, 1 ; avoid following BB optimizing away through the domination
|
|
%cond1_32 = zext i1 %cond1 to i32
|
|
callbr void asm "", "r,!i"(i32 %cond1_32) to label %outer_loop [label %return]
|
|
|
|
outer_loop:
|
|
; %cond2 = icmp eq i32 %tmp, 2
|
|
; br i1 %cond2, label %outer_loop, label %inner_loop
|
|
callbr void asm "", ""() to label %inner_loop []
|
|
|
|
inner_loop: ; preds = %LeafBlock, %LeafBlock1
|
|
store volatile i32 999, ptr addrspace(1) %out, align 4
|
|
%cond3 = icmp eq i32 %tmp, 3
|
|
%cond3_32 = zext i1 %cond3 to i32
|
|
callbr void asm "", "r,!i"(i32 %cond3_32) to label %inner_loop [label %outer_loop]
|
|
|
|
return:
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|