e95f6fa123
Introduce a target hook to incrementally flip the behavior of targets with test changes, and start by implementing it for AMDGPU. This appears to be forgotten switch flip from 2015. This seems to do a nicer job with subregister copies. Most of the test changes are improvements or neutral, not that many are light regressions. The worst AMDGPU regressions are for true16 in the atomic tests, but I think that's due to existing true16 issues.
119 lines
3.7 KiB
LLVM
119 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
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define amdgpu_kernel void @s_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
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; SI-LABEL: s_bfm_pattern:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_bfm_b32 s4, s4, s5
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: s_bfm_pattern:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_bfm_b32 s2, s2, s3
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: v_mov_b32_e32 v2, s2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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%c = shl i32 %b, %y
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store i32 %c, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
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; SI-LABEL: s_bfm_pattern_simple:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s2, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_bfm_b32 s4, s2, 0
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: s_bfm_pattern_simple:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_bfm_b32 s2, s2, 0
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: v_mov_b32_e32 v2, s2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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store i32 %b, ptr addrspace(1) %out
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ret void
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}
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define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
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; SI-LABEL: v_bfm_pattern:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_bfm_b32_e32 v2, v2, v3
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; SI-NEXT: s_mov_b32 s4, s6
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; SI-NEXT: s_mov_b32 s5, s6
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: v_bfm_pattern:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_bfm_b32 v2, v2, v3
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_setpc_b64 s[30:31]
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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%c = shl i32 %b, %y
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store i32 %c, ptr addrspace(1) %out
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ret void
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}
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define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
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; SI-LABEL: v_bfm_pattern_simple:
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; SI: ; %bb.0:
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_bfm_b32_e64 v2, v2, 0
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; SI-NEXT: s_mov_b32 s4, s6
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; SI-NEXT: s_mov_b32 s5, s6
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; SI-NEXT: s_setpc_b64 s[30:31]
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;
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; VI-LABEL: v_bfm_pattern_simple:
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; VI: ; %bb.0:
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; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VI-NEXT: v_bfm_b32 v2, v2, 0
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_setpc_b64 s[30:31]
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%a = shl i32 1, %x
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%b = sub i32 %a, 1
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store i32 %b, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind }
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