670 lines
21 KiB
C++
670 lines
21 KiB
C++
//===--- TargetDataLayout.cpp - Map Triple to LLVM data layout string -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/TargetParser/ARMTargetParser.h"
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#include "llvm/TargetParser/Triple.h"
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#include <cstring>
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using namespace llvm;
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static StringRef getManglingComponent(const Triple &T) {
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if (T.isOSBinFormatGOFF())
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return "-m:l";
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if (T.isOSBinFormatMachO())
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return "-m:o";
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if ((T.isOSWindows() || T.isUEFI()) && T.isOSBinFormatCOFF())
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return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";
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if (T.isOSBinFormatXCOFF())
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return "-m:a";
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return "-m:e";
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}
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static std::string computeARMDataLayout(const Triple &TT, StringRef ABIName) {
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auto ABI = ARM::computeTargetABI(TT, ABIName);
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std::string Ret;
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if (TT.isLittleEndian())
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// Little endian.
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Ret += "e";
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else
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// Big endian.
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Ret += "E";
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Ret += getManglingComponent(TT);
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// Pointers are 32 bits and aligned to 32 bits.
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Ret += "-p:32:32";
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// Function pointers are aligned to 8 bits (because the LSB stores the
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// ARM/Thumb state).
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Ret += "-Fi8";
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// ABIs other than APCS have 64 bit integers with natural alignment.
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if (ABI != ARM::ARM_ABI_APCS)
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Ret += "-i64:64";
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// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
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// bits, others to 64 bits. We always try to align to 64 bits.
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if (ABI == ARM::ARM_ABI_APCS)
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Ret += "-f64:32:64";
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// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
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// to 64. We always ty to give them natural alignment.
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if (ABI == ARM::ARM_ABI_APCS)
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Ret += "-v64:32:64-v128:32:128";
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else if (ABI != ARM::ARM_ABI_AAPCS16)
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Ret += "-v128:64:128";
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// Try to align aggregates to 32 bits (the default is 64 bits, which has no
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// particular hardware support on 32-bit ARM).
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Ret += "-a:0:32";
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// Integer registers are 32 bits.
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Ret += "-n32";
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// The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
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if (ABI == ARM::ARM_ABI_AAPCS16)
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Ret += "-S128";
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else if (ABI == ARM::ARM_ABI_AAPCS)
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Ret += "-S64";
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else
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Ret += "-S32";
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return Ret;
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}
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// Helper function to build a DataLayout string
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static std::string computeAArch64DataLayout(const Triple &TT) {
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if (TT.isOSBinFormatMachO()) {
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if (TT.getArch() == Triple::aarch64_32)
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return "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-"
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"n32:64-S128-Fn32";
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return "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-"
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"Fn32";
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}
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if (TT.isOSBinFormatCOFF())
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return "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-i64:64-i128:"
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"128-n32:64-S128-Fn32";
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std::string Endian = TT.isLittleEndian() ? "e" : "E";
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std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
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return Endian + "-m:e" + Ptr32 +
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"-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-"
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"n32:64-S128-Fn32";
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}
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// DataLayout: little or big endian
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static std::string computeBPFDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::bpfeb)
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return "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
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else
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return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
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}
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static std::string computeCSKYDataLayout(const Triple &TT) {
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// CSKY is always 32-bit target with the CSKYv2 ABI as prefer now.
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// It's a 4-byte aligned stack with ELF mangling only.
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// Only support little endian for now.
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// TODO: Add support for big endian.
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return "e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:32"
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"-v128:32:32-a:0:32-Fi32-n32";
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}
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static std::string computeLoongArchDataLayout(const Triple &TT) {
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if (TT.isLoongArch64())
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return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
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assert(TT.isLoongArch32() && "only LA32 and LA64 are currently supported");
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return "e-m:e-p:32:32-i64:64-n32-S128";
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}
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static std::string computeM68kDataLayout(const Triple &TT) {
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std::string Ret = "";
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// M68k is Big Endian
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Ret += "E";
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// FIXME how to wire it with the used object format?
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Ret += "-m:e";
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// M68k pointers are always 32 bit wide even for 16-bit CPUs.
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// The ABI only specifies 16-bit alignment.
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// On at least the 68020+ with a 32-bit bus, there is a performance benefit
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// to having 32-bit alignment.
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Ret += "-p:32:16:32";
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// Bytes do not require special alignment, words are word aligned and
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// long words are word aligned at minimum.
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Ret += "-i8:8:8-i16:16:16-i32:16:32";
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// FIXME no floats at the moment
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// The registers can hold 8, 16, 32 bits
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Ret += "-n8:16:32";
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Ret += "-a:0:16-S16";
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return Ret;
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}
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namespace {
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enum class MipsABI { Unknown, O32, N32, N64 };
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}
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// FIXME: This duplicates MipsABIInfo::computeTargetABI, but duplicating this is
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// preferable to violating layering rules. Ideally that information should live
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// in LLVM TargetParser, but for now we just duplicate some ABI name string
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// logic for simplicity.
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static MipsABI getMipsABI(const Triple &TT, StringRef ABIName) {
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if (ABIName.starts_with("o32"))
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return MipsABI::O32;
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if (ABIName.starts_with("n32"))
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return MipsABI::N32;
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if (ABIName.starts_with("n64"))
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return MipsABI::N64;
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if (TT.isABIN32())
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return MipsABI::N32;
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assert(ABIName.empty() && "Unknown ABI option for MIPS");
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if (TT.isMIPS64())
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return MipsABI::N64;
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return MipsABI::O32;
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}
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static std::string computeMipsDataLayout(const Triple &TT, StringRef ABIName) {
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std::string Ret;
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MipsABI ABI = getMipsABI(TT, ABIName);
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// There are both little and big endian mips.
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if (TT.isLittleEndian())
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Ret += "e";
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else
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Ret += "E";
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if (ABI == MipsABI::O32)
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Ret += "-m:m";
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else
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Ret += "-m:e";
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// Pointers are 32 bit on some ABIs.
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if (ABI != MipsABI::N64)
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Ret += "-p:32:32";
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// 8 and 16 bit integers only need to have natural alignment, but try to
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// align them to 32 bits. 64 bit integers have natural alignment.
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Ret += "-i8:8:32-i16:16:32-i64:64";
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// 32 bit registers are always available and the stack is at least 64 bit
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// aligned. On N64 64 bit registers are also available and the stack is
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// 128 bit aligned.
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if (ABI == MipsABI::N64 || ABI == MipsABI::N32)
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Ret += "-i128:128-n32:64-S128";
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else
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Ret += "-n32-S64";
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return Ret;
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}
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static std::string computePowerDataLayout(const Triple &T, StringRef ABIName) {
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bool is64Bit = T.isPPC64();
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std::string Ret;
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// Most PPC* platforms are big endian, PPC(64)LE is little endian.
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if (T.isLittleEndian())
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Ret = "e";
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else
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Ret = "E";
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Ret += getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!is64Bit || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// If the target ABI uses function descriptors, then the alignment of function
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// pointers depends on the alignment used to emit the descriptor. Otherwise,
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// function pointers are aligned to 32 bits because the instructions must be.
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if ((T.getArch() == Triple::ppc64 &&
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(!T.isPPC64ELFv2ABI() && ABIName != "elfv2"))) {
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Ret += "-Fi64";
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} else if (T.isOSAIX()) {
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Ret += is64Bit ? "-Fi64" : "-Fi32";
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} else {
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Ret += "-Fn32";
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}
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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Ret += "-i64:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (is64Bit)
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Ret += "-i128:128-n32:64";
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else
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Ret += "-n32";
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// The ABI alignment for doubles on AIX is 4 bytes.
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if (T.isOSAIX())
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Ret += "-f64:32:64";
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// Specify the vector alignment explicitly. For v256i1 and v512i1, the
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// calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
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// which is 256 and 512 bytes - way over aligned.
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if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
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Ret += "-S128-v256:256:256-v512:512:512";
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return Ret;
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}
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static std::string computeAMDDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::r600) {
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// 32-bit pointers.
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return "e-m:e-p:32:32-po2:32:32-po3:32:32-po5:32:32-i64:64"
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"-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512"
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"-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
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}
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// 32-bit private, local, and region pointers. 64-bit global, constant and
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// flat. 160-bit non-integral fat buffer pointers that include a 128-bit
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// buffer descriptor and a 32-bit offset, which are indexed by 32-bit values
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// (address space 7), and 128-bit non-integral buffer resourcees (address
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// space 8) which cannot be non-trivilally accessed by LLVM memory operations
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// like getelementptr.
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return "e-m:e-p:64:64-p1:64:64-po2:32:32-po3:32:32-p4:64:64-po5:32:32"
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"-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32"
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"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
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"-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";
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}
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static std::string computeRISCVDataLayout(const Triple &TT, StringRef ABIName) {
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if (TT.isOSBinFormatMachO()) {
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assert(TT.isLittleEndian() && "Invalid endianness");
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assert(TT.isArch32Bit() && "Invalid triple");
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assert((ABIName != "ilp32e") && "Invalid ABI.");
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return "e-m:o-p:32:32-i64:64-n32-S128";
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}
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std::string Ret;
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if (TT.isLittleEndian())
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Ret += "e";
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else
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Ret += "E";
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Ret += "-m:e";
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// TODO: Maybe we should move RISCVABI to TargetParser, so we can reuse that
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// logic here instead of duplicating the string handling?
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bool IsRVYPurecapABI =
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ABIName.starts_with("il32pc64") || ABIName.starts_with("l64pc128");
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// Pointer and integer sizes.
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if (TT.isRISCV64()) {
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Ret += "-p:64:64";
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if (IsRVYPurecapABI)
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Ret += "-pe200:128:128:128:64";
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Ret += "-i64:64-i128:128-n32:64";
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} else {
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assert(TT.isRISCV32() && "only RV32 and RV64 are currently supported");
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Ret += "-p:32:32";
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if (IsRVYPurecapABI)
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Ret += "-pe200:64:64:64:32";
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Ret += "-i64:64-n32";
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}
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// Stack alignment based on ABI.
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if (ABIName == "ilp32e")
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Ret += "-S32";
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else if (ABIName == "lp64e")
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Ret += "-S64";
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else
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Ret += "-S128";
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if (IsRVYPurecapABI)
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Ret += "-A200-P200-G200";
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return Ret;
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}
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static std::string computeSparcDataLayout(const Triple &T) {
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const bool Is64Bit = T.isSPARC64();
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// Sparc is typically big endian, but some are little.
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std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
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Ret += "-m:e";
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// Some ABIs have 32bit pointers.
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if (!Is64Bit)
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Ret += "-p:32:32";
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// Alignments for 64 bit integers.
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Ret += "-i64:64";
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// Alignments for 128 bit integers.
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// This is not specified in the ABI document but is the de facto standard.
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Ret += "-i128:128";
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// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
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// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
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if (Is64Bit)
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Ret += "-n32:64";
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else
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Ret += "-f128:64-n32";
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if (Is64Bit)
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Ret += "-S128";
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else
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Ret += "-S64";
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return Ret;
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}
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static std::string computeSystemZDataLayout(const Triple &TT) {
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std::string Ret;
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// Big endian.
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Ret += "E";
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// The natural stack alignment is 64 bits.
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Ret += "-S64";
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// Data mangling.
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Ret += getManglingComponent(TT);
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// Special features for z/OS.
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if (TT.isOSzOS()) {
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// Custom address space for ptr32.
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Ret += "-p1:32:32";
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}
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// Make sure that global data has at least 16 bits of alignment by
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// default, so that we can refer to it using LARL. We don't have any
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// special requirements for stack variables though.
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Ret += "-i1:8:16-i8:8:16";
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// 64-bit integers are naturally aligned.
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Ret += "-i64:64";
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// 128-bit floats are aligned only to 64 bits.
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Ret += "-f128:64";
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// The DataLayout string always holds a vector alignment of 64 bits, see
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// comment in clang/lib/Basic/Targets/SystemZ.h.
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Ret += "-v128:64";
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// We prefer 16 bits of aligned for all globals; see above.
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Ret += "-a:8:16";
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// Integer registers are 32 or 64 bits.
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Ret += "-n32:64";
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return Ret;
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}
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static std::string computeX86DataLayout(const Triple &TT) {
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bool Is64Bit = TT.isX86_64();
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// X86 is little endian
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std::string Ret = "e";
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Ret += getManglingComponent(TT);
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// X86 and x32 have 32 bit pointers.
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if (!Is64Bit || TT.isX32())
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Ret += "-p:32:32";
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// Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
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Ret += "-p270:32:32-p271:32:32-p272:64:64";
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// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
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// 128 bit integers are not specified in the 32-bit ABIs but are used
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// internally for lowering f128, so we match the alignment to that.
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if (Is64Bit || TT.isOSWindows())
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Ret += "-i64:64-i128:128";
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else if (TT.isOSIAMCU())
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Ret += "-i64:32-f64:32";
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else
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Ret += "-i128:128-f64:32:64";
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// Some ABIs align long double to 128 bits, others to 32.
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if (TT.isOSIAMCU())
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; // No f80
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else if (Is64Bit || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
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Ret += "-f80:128";
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else
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Ret += "-f80:32";
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if (TT.isOSIAMCU())
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Ret += "-f128:32";
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// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
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if (Is64Bit)
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Ret += "-n8:16:32:64";
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else
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Ret += "-n8:16:32";
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// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
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if ((!Is64Bit && TT.isOSWindows()) || TT.isOSIAMCU())
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Ret += "-a:0:32-S32";
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else
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Ret += "-S128";
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return Ret;
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}
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static std::string computeNVPTXDataLayout(const Triple &T, StringRef ABIName) {
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bool Is64Bit = T.getArch() == Triple::nvptx64;
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std::string Ret = "e";
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// Tensor Memory (addrspace:6) is always 32-bits.
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// Distributed Shared Memory (addrspace:7) follows shared memory
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// (addrspace:3).
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if (!Is64Bit)
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Ret += "-p:32:32-p6:32:32-p7:32:32";
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else if (ABIName == "shortptr")
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Ret += "-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32";
|
|
else
|
|
Ret += "-p6:32:32";
|
|
|
|
Ret += "-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64";
|
|
|
|
return Ret;
|
|
}
|
|
|
|
static std::string computeSPIRVDataLayout(const Triple &TT) {
|
|
const auto Arch = TT.getArch();
|
|
// TODO: this probably needs to be revisited:
|
|
// Logical SPIR-V has no pointer size, so any fixed pointer size would be
|
|
// wrong. The choice to default to 32 or 64 is just motivated by another
|
|
// memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
|
|
// mean anything.
|
|
if (Arch == Triple::spirv32)
|
|
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
|
|
"v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
|
|
if (Arch == Triple::spirv)
|
|
return "e-ve-i64:64-n8:16:32:64-G10";
|
|
if (TT.getVendor() == Triple::VendorType::AMD &&
|
|
TT.getOS() == Triple::OSType::AMDHSA)
|
|
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
|
|
"v512:512-v1024:1024-n32:64-S32-G1-P4-A0";
|
|
if (TT.getVendor() == Triple::VendorType::Intel)
|
|
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
|
|
"v512:512-v1024:1024-n8:16:32:64-G1-P9-A0";
|
|
return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
|
|
"v512:512-v1024:1024-n8:16:32:64-G1";
|
|
}
|
|
|
|
static std::string computeLanaiDataLayout() {
|
|
// Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
|
|
return "E" // Big endian
|
|
"-m:e" // ELF name manging
|
|
"-p:32:32" // 32-bit pointers, 32 bit aligned
|
|
"-i64:64" // 64 bit integers, 64 bit aligned
|
|
"-a:0:32" // 32 bit alignment of objects of aggregate type
|
|
"-n32" // 32 bit native integer width
|
|
"-S64"; // 64 bit natural stack alignment
|
|
}
|
|
|
|
static std::string computeWebAssemblyDataLayout(const Triple &TT) {
|
|
return TT.getArch() == Triple::wasm64
|
|
? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
|
|
"i128:128-f128:64-n32:64-S128-ni:1:10:20"
|
|
: "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
|
|
"i128:128-n32:64-S128-ni:1:10:20")
|
|
: (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
|
|
"i128:128-f128:64-n32:64-S128-ni:1:10:20"
|
|
: "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
|
|
"i128:128-n32:64-S128-ni:1:10:20");
|
|
}
|
|
|
|
static std::string computeVEDataLayout(const Triple &T) {
|
|
// Aurora VE is little endian
|
|
std::string Ret = "e";
|
|
|
|
// Use ELF mangling
|
|
Ret += "-m:e";
|
|
|
|
// Alignments for 64 bit integers.
|
|
Ret += "-i64:64";
|
|
|
|
// VE supports 32 bit and 64 bits integer on registers
|
|
Ret += "-n32:64";
|
|
|
|
// Stack alignment is 128 bits
|
|
Ret += "-S128";
|
|
|
|
// Vector alignments are 64 bits
|
|
// Need to define all of them. Otherwise, each alignment becomes
|
|
// the size of each data by default.
|
|
Ret += "-v64:64:64"; // for v2f32
|
|
Ret += "-v128:64:64";
|
|
Ret += "-v256:64:64";
|
|
Ret += "-v512:64:64";
|
|
Ret += "-v1024:64:64";
|
|
Ret += "-v2048:64:64";
|
|
Ret += "-v4096:64:64";
|
|
Ret += "-v8192:64:64";
|
|
Ret += "-v16384:64:64"; // for v256f64
|
|
|
|
return Ret;
|
|
}
|
|
|
|
std::string Triple::computeDataLayout(StringRef ABIName) const {
|
|
switch (getArch()) {
|
|
case Triple::arm:
|
|
case Triple::armeb:
|
|
case Triple::thumb:
|
|
case Triple::thumbeb:
|
|
return computeARMDataLayout(*this, ABIName);
|
|
case Triple::aarch64:
|
|
case Triple::aarch64_be:
|
|
case Triple::aarch64_32:
|
|
return computeAArch64DataLayout(*this);
|
|
case Triple::arc:
|
|
return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
|
|
"f32:32:32-i64:32-f64:32-a:0:32-n32";
|
|
case Triple::avr:
|
|
return "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8:16-a:8";
|
|
case Triple::bpfel:
|
|
case Triple::bpfeb:
|
|
return computeBPFDataLayout(*this);
|
|
case Triple::csky:
|
|
return computeCSKYDataLayout(*this);
|
|
case Triple::dxil:
|
|
return "e-m:e-ve-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-"
|
|
"f32:32-f64:64-n8:16:32:64";
|
|
case Triple::hexagon:
|
|
return "e-m:e-p:32:32:32-a:0-n16:32-"
|
|
"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
|
|
"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048";
|
|
case Triple::loongarch32:
|
|
case Triple::loongarch64:
|
|
return computeLoongArchDataLayout(*this);
|
|
case Triple::m68k:
|
|
return computeM68kDataLayout(*this);
|
|
case Triple::mips:
|
|
case Triple::mipsel:
|
|
case Triple::mips64:
|
|
case Triple::mips64el:
|
|
return computeMipsDataLayout(*this, ABIName);
|
|
case Triple::msp430:
|
|
return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
|
|
case Triple::ppc:
|
|
case Triple::ppcle:
|
|
case Triple::ppc64:
|
|
case Triple::ppc64le:
|
|
return computePowerDataLayout(*this, ABIName);
|
|
case Triple::r600:
|
|
case Triple::amdgcn:
|
|
return computeAMDDataLayout(*this);
|
|
case Triple::riscv32:
|
|
case Triple::riscv64:
|
|
case Triple::riscv32be:
|
|
case Triple::riscv64be:
|
|
return computeRISCVDataLayout(*this, ABIName);
|
|
case Triple::sparc:
|
|
case Triple::sparcv9:
|
|
case Triple::sparcel:
|
|
return computeSparcDataLayout(*this);
|
|
case Triple::systemz:
|
|
return computeSystemZDataLayout(*this);
|
|
case Triple::tce:
|
|
return "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-"
|
|
"f16:16:16-f32:32:32-f64:32:32-v64:64:64-i128:128-v128:128:128-"
|
|
"v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
|
|
"v4096:4096:4096-a0:0:32-n32";
|
|
case Triple::tcele:
|
|
return "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:32-"
|
|
"f16:16:16-f32:32:32-f64:32:32-v64:64:64-i128:128-v128:128:128-"
|
|
"v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
|
|
"v4096:4096:4096-a0:0:32-n32";
|
|
case Triple::tcele64:
|
|
return "e-p:64:64:64-i1:8:64-i8:8:64-i16:16:64-i32:32:64-i64:64:64-"
|
|
"f16:16:64-f32:32:64-f64:64:64-v64:64:64-i128:128-v128:128:128-"
|
|
"v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-"
|
|
"v4096:4096:4096-a0:0:64-n64";
|
|
case Triple::x86:
|
|
case Triple::x86_64:
|
|
return computeX86DataLayout(*this);
|
|
case Triple::xcore:
|
|
return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32";
|
|
case Triple::xtensa:
|
|
return "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";
|
|
case Triple::nvptx:
|
|
case Triple::nvptx64:
|
|
return computeNVPTXDataLayout(*this, ABIName);
|
|
case Triple::spir:
|
|
case Triple::spir64:
|
|
case Triple::spirv:
|
|
case Triple::spirv32:
|
|
case Triple::spirv64:
|
|
return computeSPIRVDataLayout(*this);
|
|
case Triple::lanai:
|
|
return computeLanaiDataLayout();
|
|
case Triple::wasm32:
|
|
case Triple::wasm64:
|
|
return computeWebAssemblyDataLayout(*this);
|
|
case Triple::ve:
|
|
return computeVEDataLayout(*this);
|
|
|
|
case Triple::amdil:
|
|
case Triple::amdil64:
|
|
case Triple::hsail:
|
|
case Triple::hsail64:
|
|
case Triple::kalimba:
|
|
case Triple::shave:
|
|
case Triple::renderscript32:
|
|
case Triple::renderscript64:
|
|
// These are all virtual ISAs with no LLVM backend, and therefore no fixed
|
|
// LLVM data layout.
|
|
return "";
|
|
|
|
case Triple::UnknownArch:
|
|
return "";
|
|
}
|
|
llvm_unreachable("Invalid arch");
|
|
}
|