9dc3255cb9
This switches clang to use the data layouts from TargetParser, instead of maintaining its own copy of data layouts, which are required to match the backend data layouts. For now I've kept explicit calls to resetDataLayout(), just with the argument implied by the triple and ABI. Ideally this would happen automatically, but the way these classes are initialized currently doesn't offer a great place to do this. Previously resetDataLayout() also set the UserLabelPrefix. I've separated this out, with a reasonable default so that most targets don't need to worry about it. I've kept the explicit data layouts for TCE and SPIR (without the V). These seem to not correspond to real LLVM targets. I've also fixed the XCore data layout in TargetParser, which was incorrectly set to the same one as Xtensa. It was previously unused.
123 lines
3.9 KiB
C++
123 lines
3.9 KiB
C++
//===-- XCoreTargetMachine.cpp - Define TargetMachine for XCore -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreTargetMachine.h"
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#include "TargetInfo/XCoreTargetInfo.h"
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#include "XCore.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "XCoreTargetObjectFile.h"
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#include "XCoreTargetTransformInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/Compiler.h"
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#include <optional>
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using namespace llvm;
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static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
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return RM.value_or(Reloc::Static);
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}
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static CodeModel::Model
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getEffectiveXCoreCodeModel(std::optional<CodeModel::Model> CM) {
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if (CM) {
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if (*CM != CodeModel::Small && *CM != CodeModel::Large)
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report_fatal_error("Target only supports CodeModel Small or Large");
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return *CM;
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}
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return CodeModel::Small;
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}
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/// Create an ILP32 architecture model
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///
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XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveXCoreCodeModel(CM), OL),
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TLOF(std::make_unique<XCoreTargetObjectFile>()),
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Subtarget(TT, std::string(CPU), std::string(FS), *this) {
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initAsmInfo();
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}
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XCoreTargetMachine::~XCoreTargetMachine() = default;
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namespace {
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/// XCore Code Generator Pass Configuration Options.
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class XCorePassConfig : public TargetPassConfig {
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public:
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XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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XCoreTargetMachine &getXCoreTargetMachine() const {
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return getTM<XCoreTargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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};
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} // end anonymous namespace
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TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new XCorePassConfig(*this, PM);
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}
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void XCorePassConfig::addIRPasses() {
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addPass(createAtomicExpandLegacyPass());
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TargetPassConfig::addIRPasses();
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}
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bool XCorePassConfig::addPreISel() {
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addPass(createXCoreLowerThreadLocalPass());
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return false;
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}
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bool XCorePassConfig::addInstSelector() {
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addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
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return false;
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}
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void XCorePassConfig::addPreEmitPass() {
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addPass(createXCoreFrameToArgsOffsetEliminationPass());
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}
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// Force static initialization.
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extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() {
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RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeXCoreAsmPrinterPass(PR);
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initializeXCoreDAGToDAGISelLegacyPass(PR);
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initializeXCoreLowerThreadLocalPass(PR);
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}
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TargetTransformInfo
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XCoreTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(std::make_unique<XCoreTTIImpl>(this, F));
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}
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MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo(
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BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const {
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return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI);
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}
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