ade43a54d4
Initial support for acquire-release atomics, specified as part of https://github.com/WebAssembly/shared-everything-threads This adds an ordering operand to atomic loads, stores, RMWs, wait/notify, and fences. It currently defaults to 0 and ISel is not updated yet, so atomics produced by the compiler will still always be seqcst. Asm parsing and printing, binary emission and disassembly are all updated. Binary emission will always use the old encoding because the encoding is smaller, and to get backwards compatibility for free.
144 lines
5.3 KiB
C++
144 lines
5.3 KiB
C++
//=- WebAssemblySubtarget.h - Define Subtarget for the WebAssembly -*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file declares the WebAssembly-specific subclass of
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/// TargetSubtarget.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYSUBTARGET_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYSUBTARGET_H
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyFrameLowering.h"
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#include "WebAssemblyISelLowering.h"
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#include "WebAssemblyInstrInfo.h"
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#include "WebAssemblySelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "WebAssemblyGenSubtargetInfo.inc"
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namespace llvm {
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// Defined in WebAssemblyGenSubtargetInfo.inc.
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extern const SubtargetFeatureKV
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WebAssemblyFeatureKV[WebAssembly::NumSubtargetFeatures];
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class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
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enum SIMDEnum {
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NoSIMD,
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SIMD128,
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RelaxedSIMD,
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} SIMDLevel = NoSIMD;
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bool HasAtomics = false;
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bool HasBulkMemory = false;
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bool HasBulkMemoryOpt = false;
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bool HasCallIndirectOverlong = false;
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bool HasCompactImports = false;
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bool HasExceptionHandling = false;
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bool HasExtendedConst = false;
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bool HasFP16 = false;
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bool HasGC = false;
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bool HasMultiMemory = false;
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bool HasMultivalue = false;
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bool HasMutableGlobals = false;
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bool HasNontrappingFPToInt = false;
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bool HasReferenceTypes = false;
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bool HasRelaxedAtomics = false;
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bool HasSignExt = false;
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bool HasTailCall = false;
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bool HasWideArithmetic = false;
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/// What processor and OS we're targeting.
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Triple TargetTriple;
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WebAssemblyFrameLowering FrameLowering;
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WebAssemblyInstrInfo InstrInfo;
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WebAssemblySelectionDAGInfo TSInfo;
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WebAssemblyTargetLowering TLInfo;
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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WebAssemblySubtarget &initializeSubtargetDependencies(StringRef CPU,
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StringRef FS);
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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WebAssemblySubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM);
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const WebAssemblySelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const WebAssemblyFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const WebAssemblyTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const WebAssemblyInstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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}
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const WebAssemblyRegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool enableAtomicExpand() const override;
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bool enableIndirectBrExpand() const override { return true; }
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bool enableMachineScheduler() const override;
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bool useAA() const override;
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// Predicates used by WebAssemblyInstrInfo.td.
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bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
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bool hasAtomics() const { return HasAtomics; }
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bool hasBulkMemory() const { return HasBulkMemory; }
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bool hasBulkMemoryOpt() const { return HasBulkMemoryOpt; }
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bool hasCallIndirectOverlong() const { return HasCallIndirectOverlong; }
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bool hasCompactImports() const { return HasCompactImports; }
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bool hasExceptionHandling() const { return HasExceptionHandling; }
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bool hasExtendedConst() const { return HasExtendedConst; }
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bool hasFP16() const { return HasFP16; }
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bool hasGC() const { return HasGC; }
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bool hasMultiMemory() const { return HasMultiMemory; }
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bool hasMultivalue() const { return HasMultivalue; }
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bool hasMutableGlobals() const { return HasMutableGlobals; }
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bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
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bool hasReferenceTypes() const { return HasReferenceTypes; }
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bool hasRelaxedAtomics() const { return HasRelaxedAtomics; }
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bool hasRelaxedSIMD() const { return SIMDLevel >= RelaxedSIMD; }
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bool hasSignExt() const { return HasSignExt; }
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bool hasSIMD128() const { return SIMDLevel >= SIMD128; }
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bool hasTailCall() const { return HasTailCall; }
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bool hasWideArithmetic() const { return HasWideArithmetic; }
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/// Parses features string setting specified subtarget options. Definition of
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/// function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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};
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} // end namespace llvm
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#endif
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