ade43a54d4
Initial support for acquire-release atomics, specified as part of https://github.com/WebAssembly/shared-everything-threads This adds an ordering operand to atomic loads, stores, RMWs, wait/notify, and fences. It currently defaults to 0 and ISel is not updated yet, so atomics produced by the compiler will still always be seqcst. Asm parsing and printing, binary emission and disassembly are all updated. Binary emission will always use the old encoding because the encoding is smaller, and to get backwards compatibility for free.
183 lines
7.2 KiB
TableGen
183 lines
7.2 KiB
TableGen
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This is a target description file for the WebAssembly architecture,
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/// which is also known as "wasm".
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// WebAssembly Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
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"Enable Atomics">;
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def FeatureBulkMemory :
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SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
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"Enable bulk memory operations">;
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def FeatureBulkMemoryOpt :
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SubtargetFeature<"bulk-memory-opt", "HasBulkMemoryOpt", "true",
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"Enable bulk memory optimization operations">;
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def FeatureCallIndirectOverlong :
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SubtargetFeature<"call-indirect-overlong", "HasCallIndirectOverlong", "true",
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"Enable overlong encoding for call_indirect immediates">;
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def FeatureExceptionHandling :
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SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
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"Enable Wasm exception handling">;
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def FeatureExtendedConst :
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SubtargetFeature<"extended-const", "HasExtendedConst", "true",
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"Enable extended const expressions">;
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def FeatureFP16 :
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SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable FP16 instructions">;
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def FeatureGC : SubtargetFeature<"gc", "HasGC", "true", "Enable wasm gc">;
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def FeatureMultiMemory :
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SubtargetFeature<"multimemory", "HasMultiMemory", "true",
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"Enable multiple memories">;
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def FeatureMultivalue :
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SubtargetFeature<"multivalue",
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"HasMultivalue", "true",
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"Enable multivalue blocks, instructions, and functions">;
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def FeatureMutableGlobals :
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SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
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"Enable mutable globals">;
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def FeatureNontrappingFPToInt :
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SubtargetFeature<"nontrapping-fptoint",
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"HasNontrappingFPToInt", "true",
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"Enable non-trapping float-to-int conversion operators">;
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def FeatureReferenceTypes :
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SubtargetFeature<"reference-types", "HasReferenceTypes", "true",
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"Enable reference types">;
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def FeatureRelaxedAtomics :
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SubtargetFeature<"relaxed-atomics", "HasRelaxedAtomics", "true",
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"Enable relaxed-atomics proposal">;
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def FeatureRelaxedSIMD :
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SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD",
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"Enable relaxed-simd instructions">;
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def FeatureSignExt :
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SubtargetFeature<"sign-ext", "HasSignExt", "true",
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"Enable sign extension operators">;
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def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
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"Enable 128-bit SIMD">;
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def FeatureTailCall :
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SubtargetFeature<"tail-call", "HasTailCall", "true",
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"Enable tail call instructions">;
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def FeatureWideArithmetic :
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SubtargetFeature<"wide-arithmetic", "HasWideArithmetic", "true",
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"Enable wide-arithmetic instructions">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "WebAssemblyRegisterInfo.td"
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include "WebAssemblyRegisterBanks.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrInfo.td"
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def WASM64 : HwMode<[HasAddr64]>;
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def wasm_ptr_rc : RegClassByHwMode<
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[DefaultMode, WASM64],
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[I32, I64]>;
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defm : RemapAllTargetPseudoPointerOperands<wasm_ptr_rc>;
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def WebAssemblyInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// WebAssembly Processors supported.
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//===----------------------------------------------------------------------===//
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// Minimal Viable Product.
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def : ProcessorModel<"mvp", NoSchedModel, []>;
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// Generic processor: latest stable version.
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//
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// This includes features that have achieved phase 4 of the standards process,
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// and that are expected to work for most users in the current time, with
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// consideration given to available support in relevant engines and tools, and
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// the importance of the features.
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def : ProcessorModel<"generic", NoSchedModel,
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[FeatureBulkMemory, FeatureBulkMemoryOpt,
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FeatureCallIndirectOverlong, FeatureMultivalue,
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FeatureMutableGlobals, FeatureNontrappingFPToInt,
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FeatureReferenceTypes, FeatureSignExt]>;
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// Lime1: <https://github.com/WebAssembly/tool-conventions/blob/main/Lime.md#lime1>
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def : ProcessorModel<"lime1", NoSchedModel,
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[FeatureBulkMemoryOpt, FeatureCallIndirectOverlong,
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FeatureExtendedConst, FeatureMultivalue,
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FeatureMutableGlobals, FeatureNontrappingFPToInt,
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FeatureSignExt]>;
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// Latest and greatest experimental version of WebAssembly. Bugs included!
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def : ProcessorModel<"bleeding-edge", NoSchedModel,
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[FeatureAtomics, FeatureBulkMemory, FeatureBulkMemoryOpt,
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FeatureCallIndirectOverlong, FeatureExceptionHandling,
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FeatureExtendedConst, FeatureFP16, FeatureGC,
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FeatureMultiMemory, FeatureMultivalue, FeatureMutableGlobals,
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FeatureNontrappingFPToInt, FeatureRelaxedSIMD,
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FeatureReferenceTypes, FeatureSIMD128,
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FeatureSignExt, FeatureTailCall]>;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def WebAssemblyAsmParser : AsmParser {
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// The physical register names are not in the binary format or asm text
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let ShouldEmitMatchRegisterName = 0;
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}
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def WebAssemblyAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def WebAssembly : Target {
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let InstructionSet = WebAssemblyInstrInfo;
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let AssemblyParsers = [WebAssemblyAsmParser];
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let AssemblyWriters = [WebAssemblyAsmWriter];
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}
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