472c8f8d96
There may be some BB to COPY fgr64cc register, and the fgr64cc register is set by the previous BB. We add a new pass called MipsSetMachineRegisterFlags, in which we set We introduce a new pass called MipsSetMachineRegisterFlags, in which we set NoSWrap flag for all instructions that works with fgr64cc registers. And in copyPhyRegister, we allow the COPY instruction with NoSignWrap from the double float registers to gpr32.
338 lines
13 KiB
C++
338 lines
13 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetMachine.h"
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "Mips.h"
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#include "Mips16ISelDAGToDAG.h"
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#include "MipsMachineFunction.h"
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#include "MipsSEISelDAGToDAG.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetObjectFile.h"
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#include "MipsTargetTransformInfo.h"
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#include "TargetInfo/MipsTargetInfo.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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#include <optional>
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#include <string>
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using namespace llvm;
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#define DEBUG_TYPE "mips"
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static cl::opt<bool>
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EnableMulMulFix("mfix4300", cl::init(false),
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cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden);
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extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
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RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
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RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
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RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
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PassRegistry *PR = PassRegistry::getPassRegistry();
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initializeGlobalISel(*PR);
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initializeMipsAsmPrinterPass(*PR);
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initializeMipsDelaySlotFillerPass(*PR);
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initializeMipsBranchExpansionPass(*PR);
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initializeMicroMipsSizeReducePass(*PR);
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initializeMipsPreLegalizerCombinerPass(*PR);
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initializeMipsPostLegalizerCombinerPass(*PR);
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initializeMipsMulMulBugFixPass(*PR);
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initializeMipsDAGToDAGISelLegacyPass(*PR);
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initializeMipsSetMachineRegisterFlagsPass(*PR);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatCOFF())
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return std::make_unique<TargetLoweringObjectFileCOFF>();
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return std::make_unique<MipsTargetObjectFile>();
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}
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static Reloc::Model getEffectiveRelocModel(bool JIT,
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std::optional<Reloc::Model> RM) {
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if (!RM || JIT)
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return Reloc::Static;
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return *RM;
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}
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT,
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bool isLittle)
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: CodeGenTargetMachineImpl(
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T, TT.computeDataLayout(Options.MCOptions.getABIName()), TT, CPU, FS,
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Options, getEffectiveRelocModel(JIT, RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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isLittle(isLittle), TLOF(createTLOF(getTargetTriple())),
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ABI(MipsABIInfo::computeTargetABI(TT, Options.MCOptions.getABIName())),
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Subtarget(nullptr),
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DefaultSubtarget(TT, CPU, FS, isLittle, *this, std::nullopt),
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NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
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isLittle, *this, std::nullopt),
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Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
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isLittle, *this, std::nullopt) {
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Subtarget = &DefaultSubtarget;
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initAsmInfo();
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// Mips supports the debug entry values.
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setSupportsDebugEntryValues(true);
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}
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MipsTargetMachine::~MipsTargetMachine() = default;
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void MipsebTargetMachine::anchor() {}
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MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
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void MipselTargetMachine::anchor() {}
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MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
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const MipsSubtarget *
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MipsTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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bool hasMips16Attr = F.getFnAttribute("mips16").isValid();
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bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid();
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bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid();
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bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid();
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function, so we can enable it as a subtarget feature.
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bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
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if (hasMips16Attr)
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FS += FS.empty() ? "+mips16" : ",+mips16";
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else if (hasNoMips16Attr)
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FS += FS.empty() ? "-mips16" : ",-mips16";
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if (HasMicroMipsAttr)
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FS += FS.empty() ? "+micromips" : ",+micromips";
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else if (HasNoMicroMipsAttr)
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FS += FS.empty() ? "-micromips" : ",-micromips";
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if (softFloat)
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FS += FS.empty() ? "+soft-float" : ",+soft-float";
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = std::make_unique<MipsSubtarget>(
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TargetTriple, CPU, FS, isLittle, *this,
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MaybeAlign(F.getParent()->getOverrideStackAlignment()));
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}
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return I.get();
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}
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void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
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LLVM_DEBUG(dbgs() << "resetSubtarget\n");
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Subtarget = &MF->getSubtarget<MipsSubtarget>();
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}
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namespace {
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// The current implementation of long branch pass requires a scratch
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// register ($at) to be available before branch instructions. Tail merging
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// can break this requirement, so disable it when long branch pass is
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// enabled.
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EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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EnableLoopTermFold = true;
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}
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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void addPreRegBankSelect() override;
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bool addRegBankSelect() override;
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bool addGlobalInstructionSelect() override;
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std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
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};
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} // end anonymous namespace
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(*this, PM);
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}
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std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
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return getStandardCSEConfigForOpt(TM->getOptLevel());
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}
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void MipsPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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addPass(createAtomicExpandLegacyPass());
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if (getMipsSubtarget().os16())
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addPass(createMipsOs16Pass());
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if (getMipsSubtarget().inMips16HardFloat())
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addPass(createMips16HardFloatPass());
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector() {
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addPass(createMipsModuleISelDagPass());
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addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
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addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
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return false;
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}
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void MipsPassConfig::addPreRegAlloc() {
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addPass(createMipsOptimizePICCallPass());
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addPass(createMipsSetMachineRegisterFlagsPass());
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}
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TargetTransformInfo
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MipsTargetMachine::getTargetTransformInfo(const Function &F) const {
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if (Subtarget->allowMixed16_32()) {
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LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
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// FIXME: This is no longer necessary as the TTI returned is per-function.
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return TargetTransformInfo(F.getDataLayout());
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}
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LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
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return TargetTransformInfo(std::make_unique<MipsTTIImpl>(this, F));
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}
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MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo(
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BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const {
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return MipsFunctionInfo::create<MipsFunctionInfo>(Allocator, F, STI);
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted.
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void MipsPassConfig::addPreEmitPass() {
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// Expand pseudo instructions that are sensitive to register allocation.
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addPass(createMipsExpandPseudoPass());
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// The microMIPS size reduction pass performs instruction reselection for
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// instructions which can be remapped to a 16 bit instruction.
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addPass(createMicroMipsSizeReducePass());
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// This pass inserts a nop instruction between two back-to-back multiplication
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// instructions when the "mfix4300" flag is passed.
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if (EnableMulMulFix)
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addPass(createMipsMulMulBugPass());
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// The delay slot filler pass can potientially create forbidden slot hazards
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// for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
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addPass(createMipsDelaySlotFillerPass());
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// This pass expands branches and takes care about the forbidden slot hazards.
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// Expanding branches may potentially create forbidden slot hazards for
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// MIPSR6, and fixing such hazard may potentially break a branch by extending
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// its offset out of range. That's why this pass combine these two tasks, and
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// runs them alternately until one of them finishes without any changes. Only
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// then we can be sure that all branches are expanded properly and no hazards
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// exists.
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// Any new pass should go before this pass.
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addPass(createMipsBranchExpansion());
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addPass(createMipsConstantIslandPass());
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}
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bool MipsPassConfig::addIRTranslator() {
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addPass(new IRTranslator(getOptLevel()));
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return false;
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}
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void MipsPassConfig::addPreLegalizeMachineIR() {
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addPass(createMipsPreLegalizeCombiner());
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}
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bool MipsPassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;
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}
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void MipsPassConfig::addPreRegBankSelect() {
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bool IsOptNone = getOptLevel() == CodeGenOptLevel::None;
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addPass(createMipsPostLegalizeCombiner(IsOptNone));
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}
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bool MipsPassConfig::addRegBankSelect() {
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addPass(new RegBankSelect());
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return false;
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}
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bool MipsPassConfig::addGlobalInstructionSelect() {
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addPass(new InstructionSelect(getOptLevel()));
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return false;
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}
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