f3efbce4a7
Clang and other frontends generally need the LLVM data layout string in
order to generate LLVM IR modules for LLVM. MLIR clients often need it
as well, since MLIR users often lower to LLVM IR.
Before this change, the LLVM datalayout string was computed in the
LLVM${TGT}CodeGen library in the relevant TargetMachine subclass.
However, none of the logic for computing the data layout string requires
any details of code generation. Clients who want to avoid duplicating
this information were forced to link in LLVMCodeGen and all registered
targets, leading to bloated binaries. This happened in PR #145899,
which measurably increased binary size for some of our users.
By moving this information to the TargetParser library, we
can delete the duplicate datalayout strings in Clang, and retain the
ability to generate IR for unregistered targets.
This is intended to be a very mechanical LLVM-only change, but there is
an immediately obvious follow-up to clang, which will be prepared
separately.
The vast majority of data layouts are computable with two inputs: the
triple and the "ABI name". There is only one exception, NVPTX, which has
a cl::opt to enable short device pointers. I invented a "shortptr" ABI
name to pass this option through the target independent interface.
Everything else fits. Mips is a bit awkward because it uses a special
MipsABIInfo abstraction, which includes members with codegen-like
concepts like ABI physical registers that can't live in TargetParser. I
think the string logic of looking for "n32" "n64" etc is reasonable to
duplicate. We have plenty of other minor duplication to preserve
layering.
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
143 lines
4.5 KiB
C++
143 lines
4.5 KiB
C++
//===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AVR specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRTargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Compiler.h"
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#include "AVR.h"
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#include "AVRMachineFunctionInfo.h"
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#include "AVRTargetObjectFile.h"
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#include "AVRTargetTransformInfo.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "TargetInfo/AVRTargetInfo.h"
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#include <optional>
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namespace llvm {
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/// Processes a CPU name.
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static StringRef getCPU(StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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return "avr2";
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}
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return CPU;
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}
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static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
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return RM.value_or(Reloc::Static);
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}
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AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: CodeGenTargetMachineImpl(T, TT.computeDataLayout(), TT, getCPU(CPU), FS,
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Options, getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {
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this->TLOF = std::make_unique<AVRTargetObjectFile>();
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initAsmInfo();
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}
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namespace {
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/// AVR Code Generator Pass Configuration Options.
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class AVRPassConfig : public TargetPassConfig {
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public:
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AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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EnableLoopTermFold = true;
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}
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AVRTargetMachine &getAVRTargetMachine() const {
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return getTM<AVRTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AVRPassConfig(*this, PM);
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}
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void AVRPassConfig::addIRPasses() {
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// Expand instructions like
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// %result = shl i32 %n, %amount
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// to a loop so that library calls are avoided.
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addPass(createAVRShiftExpandPass());
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TargetPassConfig::addIRPasses();
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}
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extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
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// Register the target.
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RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
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auto &PR = *PassRegistry::getPassRegistry();
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initializeAVRAsmPrinterPass(PR);
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initializeAVRExpandPseudoPass(PR);
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initializeAVRShiftExpandPass(PR);
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initializeAVRDAGToDAGISelLegacyPass(PR);
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
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return &SubTarget;
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
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return &SubTarget;
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}
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TargetTransformInfo
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AVRTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(std::make_unique<AVRTTIImpl>(this, F));
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}
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MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo(
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BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const {
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return AVRMachineFunctionInfo::create<AVRMachineFunctionInfo>(Allocator, F,
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STI);
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool AVRPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
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// Create the frame analyzer pass used by the PEI pass.
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addPass(createAVRFrameAnalyzerPass());
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return false;
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}
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void AVRPassConfig::addPreSched2() { addPass(createAVRExpandPseudoPass()); }
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void AVRPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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addPass(&BranchRelaxationPassID);
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}
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} // end of namespace llvm
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