f8416c8643
This patch replaces DivergentValues with UniformValues as the single source of truth for tracking divergence in UniformityInfo. Old model: DivergentValues starts empty; values are added as divergence is propagated. isDivergent(V) returns DivergentValues.count(V). New model: UniformValues starts fully populated (all instructions/arguments for IR, all register defs for MIR) during initialize(). Values are removed as divergence is propagated. isDivergent(V) returns !UniformValues.contains(V), so any value not present in the set (e.g., a newly created instruction that was not present during analysis) is conservatively treated as divergent. This avoids silent miscompilations when transformation passes introduce new values and query their uniformity. --------- Co-authored-by: padivedi <padivedi@amd.com>
126 lines
4.1 KiB
C++
126 lines
4.1 KiB
C++
//===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a specialization of the GenericSSAContext<X>
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/// template class for Machine IR.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineSSAContext.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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template <>
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void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
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const MachineBasicBlock &block) {
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for (auto &instr : block.instrs()) {
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for (auto &op : instr.all_defs())
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defs.push_back(op.getReg());
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}
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}
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template <>
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void MachineSSAContext::appendBlockTerms(SmallVectorImpl<MachineInstr *> &terms,
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MachineBasicBlock &block) {
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for (auto &T : block.terminators())
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terms.push_back(&T);
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}
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template <>
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void MachineSSAContext::appendBlockTerms(
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SmallVectorImpl<const MachineInstr *> &terms,
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const MachineBasicBlock &block) {
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for (auto &T : block.terminators())
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terms.push_back(&T);
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}
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/// Get the defining block of a value.
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template <>
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const MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const {
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if (!value)
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return nullptr;
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return F->getRegInfo().getVRegDef(value)->getParent();
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}
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static bool isUndef(const MachineInstr &MI) {
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return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
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MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
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}
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template <> bool MachineSSAContext::isAlwaysUniform(Register) { return false; }
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/// MachineInstr equivalent of PHINode::hasConstantOrUndefValue() for G_PHI.
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template <>
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bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) {
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if (!Phi.isPHI())
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return false;
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// In later passes PHI may appear with an undef operand, getVRegDef can fail.
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if (Phi.getOpcode() == TargetOpcode::PHI)
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return Phi.isConstantValuePHI().isValid();
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// For G_PHI we do equivalent of PHINode::hasConstantOrUndefValue().
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const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo();
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Register This = Phi.getOperand(0).getReg();
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Register ConstantValue;
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for (unsigned i = 1, e = Phi.getNumOperands(); i < e; i += 2) {
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Register Incoming = Phi.getOperand(i).getReg();
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if (Incoming != This && !isUndef(*MRI.getVRegDef(Incoming))) {
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if (ConstantValue && ConstantValue != Incoming)
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return false;
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ConstantValue = Incoming;
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}
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}
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return true;
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}
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template <>
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Intrinsic::ID MachineSSAContext::getIntrinsicID(const MachineInstr &MI) {
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if (auto *GI = dyn_cast<GIntrinsic>(&MI))
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return GI->getIntrinsicID();
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return Intrinsic::not_intrinsic;
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}
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template <>
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Printable MachineSSAContext::print(const MachineBasicBlock *Block) const {
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if (!Block)
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return Printable([](raw_ostream &Out) { Out << "<nullptr>"; });
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return Printable([Block](raw_ostream &Out) { Block->printName(Out); });
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}
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template <> Printable MachineSSAContext::print(const MachineInstr *I) const {
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return Printable([I](raw_ostream &Out) { I->print(Out); });
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}
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template <> Printable MachineSSAContext::print(Register Value) const {
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auto *MRI = &F->getRegInfo();
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return Printable([MRI, Value](raw_ostream &Out) {
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Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI);
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if (Value) {
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// Try to print the definition.
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if (auto *Instr = MRI->getUniqueVRegDef(Value)) {
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Out << ": ";
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Instr->print(Out);
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}
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}
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});
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}
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template <>
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Printable MachineSSAContext::printAsOperand(const MachineBasicBlock *BB) const {
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return Printable([BB](raw_ostream &Out) { BB->printAsOperand(Out); });
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}
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