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[AArch64][llvm] Armv9.7-A: Add support for Memory Partitioning and Management (FEAT_MPAMv2) (#163157)

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Add new instructions and system registers for `FEAT_MPAMv2`:
  * MLBI ALLE1
  * MLBI VMALLE1
  * MLBI VPIDE1, <Xt>
  * MLBI VPMGE1, <Xt>

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
This commit is contained in:
Jonathan Thackray
2025-10-23 23:35:37 +01:00
committed by GitHub
parent 66e8270e8f
commit d30f18d2cd
14 changed files with 276 additions and 72 deletions
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4
clang/test/Driver/aarch64-v97a.c
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@@ -29,3 +29,7 @@
// RUN: %clang -target aarch64 -march=armv9.7a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
// RUN: %clang -target aarch64 -march=armv9.7-a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
// V97A-TLBID: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tlbid"
// RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
// V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"

1
clang/test/Driver/print-supported-extensions-aarch64.c
View File

@@ -45,6 +45,7 @@
// CHECK-NEXT: lsui FEAT_LSUI Enable Armv9.6-A unprivileged load/store instructions
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
// CHECK-NEXT: mpamv2 FEAT_MPAMv2 Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations

3
llvm/lib/Target/AArch64/AArch64Features.td
View File

@@ -598,6 +598,9 @@ def FeatureLSCP : ExtensionWithMArch<"lscp", "LSCP", "FEAT_LSCP",
def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
"Enable Armv9.7-A TLBI Domains extension">;
def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
"Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;
//===----------------------------------------------------------------------===//
// Other Features
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@@ -402,6 +402,8 @@ def HasCPA : Predicate<"Subtarget->hasCPA()">,
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
def HasMPAMv2 : Predicate<"Subtarget->hasMPAMv2()">,
AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;

59
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@@ -1880,12 +1880,6 @@ def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
// v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMPAM} }] in {
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>;
def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>;
def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>;
@@ -1895,7 +1889,6 @@ def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>;
def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>;
def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>;
def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>;
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
} //FeatureMPAM
// v8.4a Activity Monitor registers
@@ -2336,6 +2329,26 @@ def : RWSysReg<"MPAMBW0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b101>;
def : RWSysReg<"MPAMBWCAP_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b110>;
def : RWSysReg<"MPAMBWSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b111>;
// v9.7a Memory partitioning and monitoring version 2
// (FEAT_MPAMv2) registers
// Op0 Op1 CRn CRm Op2
// MPAM system registers that are also available for MPAMv2
def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>;
def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>;
def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>;
def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>;
// Only MPAMv2 registers
def : RWSysReg<"MPAMCTL_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMCTL_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b010>;
def : RWSysReg<"MPAMVIDCR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b000>;
def : RWSysReg<"MPAMVIDSR_EL2", 0b11, 0b100, 0b1010, 0b0111, 0b001>;
def : RWSysReg<"MPAMVIDSR_EL3", 0b11, 0b110, 0b1010, 0b0111, 0b001>;
//===----------------------------------------------------------------------===//
// FEAT_SRMASK v9.6a registers
//===----------------------------------------------------------------------===//
@@ -2442,3 +2455,35 @@ foreach n = 0-3 in {
}
def : ROSysReg<"TLBIDIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b110>;
// MPAM Lookaside Buffer Invalidate (MLBI) instructions
class MLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
let Encoding{6-3} = crm;
let Encoding{2-0} = op2;
bit NeedsReg = needsreg;
string RequiresStr = [{ {AArch64::FeatureMPAMv2} }];
}
def MLBITable : GenericTable {
let FilterClass = "MLBI";
let CppTypeName = "MLBI";
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
let PrimaryKey = ["Encoding"];
let PrimaryKeyName = "lookupMLBIByEncoding";
}
def lookupMLBIByName : SearchIndex {
let Table = MLBITable;
let Key = ["Name"];
}
// Op1 CRn CRm Op2 needsReg
def : MLBI<"ALLE1", 0b100, 0b0111, 0b0000, 0b100, 0>;
def : MLBI<"VMALLE1", 0b100, 0b0111, 0b0000, 0b101, 0>;
def : MLBI<"VPIDE1", 0b100, 0b0111, 0b0000, 0b110, 1>;
def : MLBI<"VPMGE1", 0b100, 0b0111, 0b0000, 0b111, 1>;

27
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@@ -3886,6 +3886,7 @@ static const struct Extension {
{"cmh", {AArch64::FeatureCMH}},
{"lscp", {AArch64::FeatureLSCP}},
{"tlbid", {AArch64::FeatureTLBID}},
{"mpamv2", {AArch64::FeatureMPAMv2}},
};
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -3958,8 +3959,9 @@ void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands
AArch64Operand::CreateImm(Expr, S, getLoc(), getContext()));
}
/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
/// the SYS instruction. Parse them specially so that we create a SYS MCInst.
/// parseSysAlias - The IC, DC, AT, TLBI, and MLBI instructions
/// are simple aliases for the SYS instruction. Parse them specially so that
/// we create a SYS MCInst.
bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
OperandVector &Operands) {
if (Name.contains('.'))
@@ -4021,7 +4023,19 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
OptionalRegister = TLBI->OptionalReg;
}
createSysAlias(TLBI->Encoding, Operands, S);
} else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" || Mnemonic == "cosp") {
} else if (Mnemonic == "mlbi") {
const AArch64MLBI::MLBI *MLBI = AArch64MLBI::lookupMLBIByName(Op);
if (!MLBI)
return TokError("invalid operand for MLBI instruction");
else if (!MLBI->haveFeatures(getSTI().getFeatureBits())) {
std::string Str("MLBI " + std::string(MLBI->Name) + " requires: ");
setRequiredFeatureString(MLBI->getRequiredFeatures(), Str);
return TokError(Str);
}
ExpectRegister = MLBI->NeedsReg;
createSysAlias(MLBI->Encoding, Operands, S);
} else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" ||
Mnemonic == "cosp") {
if (Op.lower() != "rctx")
return TokError("invalid operand for prediction restriction instruction");
@@ -5338,10 +5352,11 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next);
// IC, DC, AT, TLBI and Prediction invalidation instructions are aliases for
// the SYS instruction.
// IC, DC, AT, TLBI, MLBI and Prediction invalidation instructions are aliases
// for the SYS instruction.
if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi" ||
Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp")
Head == "cfp" || Head == "dvp" || Head == "cpp" || Head == "cosp" ||
Head == "mlbi")
return parseSysAlias(Head, NameLoc, Operands);
// TLBIP instructions are aliases for the SYSP instruction.

11
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
View File

@@ -917,6 +917,17 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
if (CnVal == 7) {
switch (CmVal) {
default: return false;
// MLBI aliases
case 0: {
const AArch64MLBI::MLBI *MLBI =
AArch64MLBI::lookupMLBIByEncoding(Encoding);
if (!MLBI || !MLBI->haveFeatures(STI.getFeatureBits()))
return false;
NeedsReg = MLBI->NeedsReg;
Ins = "mlbi\t";
Name = std::string(MLBI->Name);
} break;
// Maybe IC, maybe Prediction Restriction
case 1:
switch (Op1Val) {

5
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
View File

@@ -197,6 +197,11 @@ namespace AArch64TLBIP {
#define GET_TLBIPTable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP
namespace AArch64MLBI {
#define GET_MLBITable_IMPL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64MLBI
} // namespace llvm
namespace llvm {

8
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
View File

@@ -821,6 +821,14 @@ struct TLBIP : SysAliasOptionalReg {
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64TLBIP
namespace AArch64MLBI {
struct MLBI : SysAliasReg {
using SysAliasReg::SysAliasReg;
};
#define GET_MLBITable_DECL
#include "AArch64GenSystemOperands.inc"
} // namespace AArch64MLBI
namespace AArch64II {
/// Target Operand Flag enum.
enum TOF {

48
llvm/test/MC/AArch64/armv8.4a-mpam.s
View File

@@ -1,5 +1,4 @@
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK
// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
@@ -56,9 +55,6 @@ mrs x0, MPAMIDR_EL1
//CHECK: msr MPAMVPM6_EL2, x0 // encoding: [0xc0,0xa6,0x1c,0xd5]
//CHECK: msr MPAMVPM7_EL2, x0 // encoding: [0xe0,0xa6,0x1c,0xd5]
//CHECK-RO: error: expected writable system register or pstate
//CHECK-RO: msr MPAMIDR_EL1, x0
//CHECK-RO: ^
//CHECK: mrs x0, MPAM0_EL1 // encoding: [0x20,0xa5,0x38,0xd5]
//CHECK: mrs x0, MPAM1_EL1 // encoding: [0x00,0xa5,0x38,0xd5]
@@ -77,24 +73,7 @@ mrs x0, MPAMIDR_EL1
//CHECK: mrs x0, MPAMVPM7_EL2 // encoding: [0xe0,0xa6,0x3c,0xd5]
//CHECK: mrs x0, MPAMIDR_EL1 // encoding: [0x80,0xa4,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM0_EL1, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM1_EL1, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM2_EL2, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM3_EL3, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAM1_EL12, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMHCR_EL2, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMVPMV_EL2, x0
//CHECK-ERROR: ^
@@ -122,28 +101,8 @@ mrs x0, MPAMIDR_EL1
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMVPM7_EL2, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: msr MPAMIDR_EL1, x0
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM0_EL1
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM1_EL1
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM2_EL2
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM3_EL3
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAM1_EL12
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMHCR_EL2
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMVPMV_EL2
//CHECK-ERROR: ^
@@ -171,6 +130,3 @@ mrs x0, MPAMIDR_EL1
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMVPM7_EL2
//CHECK-ERROR: ^
//CHECK-ERROR: error: expected readable system register
//CHECK-ERROR: mrs x0, MPAMIDR_EL1
//CHECK-ERROR: ^

18
llvm/test/MC/AArch64/armv9.7a-mpamv2-diagnostics.s Normal file
View File

@@ -0,0 +1,18 @@
// RUN: not llvm-mc -triple=aarch64 -mattr=+mpamv2 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
// Armv9.7-A FEAT_MPAMV2 Extensions
//------------------------------------------------------------------------------
mlbi alle1, x30
// CHECK-ERROR: error: specified mlbi op does not use a register
mlbi vmalle1, x30
// CHECK-ERROR: error: specified mlbi op does not use a register
mlbi vpide1
// CHECK-ERROR: error: specified mlbi op requires a register
mlbi vpmge1
// CHECK-ERROR: error: specified mlbi op requires a register

126
llvm/test/MC/AArch64/armv9.7a-mpamv2.s Normal file
View File

@@ -0,0 +1,126 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \
// RUN: | llvm-objdump -d --mattr=+mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mpamv2 < %s \
// RUN: | llvm-objdump -d --mattr=-mpamv2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mpamv2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+mpamv2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
//------------------------------------------------------------------------------
// Armv9.7-A FEAT_MPAMV2 Extensions
//------------------------------------------------------------------------------
msr MPAMCTL_EL1, x0
// CHECK-INST: msr MPAMCTL_EL1, x0
// CHECK-ENCODING: [0x40,0xa5,0x18,0xd5]
// CHECK-UNKNOWN: d518a540
msr MPAMCTL_EL12, x0
// CHECK-INST: msr MPAMCTL_EL12, x0
// CHECK-ENCODING: [0x40,0xa5,0x1d,0xd5]
// CHECK-UNKNOWN: d51da540
msr MPAMCTL_EL2, x0
// CHECK-INST: msr MPAMCTL_EL2, x0
// CHECK-ENCODING: [0x40,0xa5,0x1c,0xd5]
// CHECK-UNKNOWN: d51ca540
msr MPAMCTL_EL3, x0
// CHECK-INST: msr MPAMCTL_EL3, x0
// CHECK-ENCODING: [0x40,0xa5,0x1e,0xd5]
// CHECK-UNKNOWN: d51ea540
msr MPAMVIDCR_EL2, x0
// CHECK-INST: msr MPAMVIDCR_EL2, x0
// CHECK-ENCODING: [0x00,0xa7,0x1c,0xd5]
// CHECK-UNKNOWN: d51ca700
msr MPAMVIDSR_EL2, x0
// CHECK-INST: msr MPAMVIDSR_EL2, x0
// CHECK-ENCODING: [0x20,0xa7,0x1c,0xd5]
// CHECK-UNKNOWN: d51ca720
msr MPAMVIDSR_EL3, x0
// CHECK-INST: msr MPAMVIDSR_EL3, x0
// CHECK-ENCODING: [0x20,0xa7,0x1e,0xd5]
// CHECK-UNKNOWN: d51ea720
mrs x0, MPAMCTL_EL1
// CHECK-INST: mrs x0, MPAMCTL_EL1
// CHECK-ENCODING: [0x40,0xa5,0x38,0xd5]
// CHECK-UNKNOWN: d538a540
mrs x0, MPAMCTL_EL12
// CHECK-INST: mrs x0, MPAMCTL_EL12
// CHECK-ENCODING: [0x40,0xa5,0x3d,0xd5]
// CHECK-UNKNOWN: d53da540
mrs x0, MPAMCTL_EL2
// CHECK-INST: mrs x0, MPAMCTL_EL2
// CHECK-ENCODING: [0x40,0xa5,0x3c,0xd5]
// CHECK-UNKNOWN: d53ca540
mrs x0, MPAMCTL_EL3
// CHECK-INST: mrs x0, MPAMCTL_EL3
// CHECK-ENCODING: [0x40,0xa5,0x3e,0xd5]
// CHECK-UNKNOWN: d53ea540
mrs x0, MPAMVIDCR_EL2
// CHECK-INST: mrs x0, MPAMVIDCR_EL2
// CHECK-ENCODING: [0x00,0xa7,0x3c,0xd5]
// CHECK-UNKNOWN: d53ca700
mrs x0, MPAMVIDSR_EL2
// CHECK-INST: mrs x0, MPAMVIDSR_EL2
// CHECK-ENCODING: [0x20,0xa7,0x3c,0xd5]
// CHECK-UNKNOWN: d53ca720
mrs x0, MPAMVIDSR_EL3
// CHECK-INST: mrs x0, MPAMVIDSR_EL3
// CHECK-ENCODING: [0x20,0xa7,0x3e,0xd5]
// CHECK-UNKNOWN: d53ea720
//------------------------------------------------------------------------------
// Armv9.7-A FEAT_MPAMV2_VID Extensions
//------------------------------------------------------------------------------
mlbi vmalle1
// CHECK-INST: mlbi vmalle1
// CHECK-ENCODING: [0xbf,0x70,0x0c,0xd5]
// CHECK-UNKNOWN: d50c70bf sys #4, c7, c0, #5
// CHECK-ERROR: error: MLBI VMALLE1 requires: mpamv2
mlbi vpide1, x0
// CHECK-INST: mlbi vpide1, x0
// CHECK-ENCODING: [0xc0,0x70,0x0c,0xd5]
// CHECK-UNKNOWN: d50c70c0 sys #4, c7, c0, #6, x0
// CHECK-ERROR: error: MLBI VPIDE1 requires: mpamv2
mlbi vpmge1, x0
// CHECK-INST: mlbi vpmge1, x0
// CHECK-ENCODING: [0xe0,0x70,0x0c,0xd5]
// CHECK-UNKNOWN: d50c70e0 sys #4, c7, c0, #7, x0
// CHECK-ERROR: error: MLBI VPMGE1 requires: mpamv2
// Check that invalid encodings are rendered as SYS aliases
// [0x9f,0x70,0x0c,0xd5] -> mlbi alle1
// [0x9e,0x70,0x0c,0xd5] -> sys #4, c7, c0, #4, x30
mlbi alle1
// CHECK-INST: mlbi alle1
// CHECK-ENCODING: [0x9f,0x70,0x0c,0xd5]
// CHECK-UNKNOWN: d50c709f sys #4, c7, c0, #4
// CHECK-ERROR: error: MLBI ALLE1 requires: mpamv2
sys #4, c7, c0, #4, x30
// CHECK-INST: sys #4, c7, c0, #4, x30
// CHECK-ENCODING: [0x9e,0x70,0x0c,0xd5]
// CHECK-UNKNOWN: d50c709e sys #4, c7, c0, #4, x30

33
llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
View File

@@ -65,12 +65,14 @@
#CHECK: mrs x0, MPAMVPM7_EL2
#CHECK: mrs x0, MPAMIDR_EL1
#CHECK-NOV84: msr S3_0_C10_C5_1, x0
#CHECK-NOV84: msr S3_0_C10_C5_0, x0
#CHECK-NOV84: msr S3_4_C10_C5_0, x0
#CHECK-NOV84: msr S3_6_C10_C5_0, x0
#CHECK-NOV84: msr S3_5_C10_C5_0, x0
#CHECK-NOV84: msr S3_4_C10_C4_0, x0
// Available outside MPAM from Armv9.7
#CHECK-NOV84: msr MPAM0_EL1, x0
#CHECK-NOV84: msr MPAM1_EL1, x0
#CHECK-NOV84: msr MPAM2_EL2, x0
#CHECK-NOV84: msr MPAM3_EL3, x0
#CHECK-NOV84: msr MPAM1_EL12, x0
#CHECK-NOV84: msr MPAMHCR_EL2, x0
#CHECK-NOV84: msr S3_4_C10_C4_1, x0
#CHECK-NOV84: msr S3_4_C10_C6_0, x0
#CHECK-NOV84: msr S3_4_C10_C6_1, x0
@@ -80,12 +82,15 @@
#CHECK-NOV84: msr S3_4_C10_C6_5, x0
#CHECK-NOV84: msr S3_4_C10_C6_6, x0
#CHECK-NOV84: msr S3_4_C10_C6_7, x0
#CHECK-NOV84: mrs x0, S3_0_C10_C5_1
#CHECK-NOV84: mrs x0, S3_0_C10_C5_0
#CHECK-NOV84: mrs x0, S3_4_C10_C5_0
#CHECK-NOV84: mrs x0, S3_6_C10_C5_0
#CHECK-NOV84: mrs x0, S3_5_C10_C5_0
#CHECK-NOV84: mrs x0, S3_4_C10_C4_0
// Available outside MPAM from Armv9.7
#CHECK-NOV84: mrs x0, MPAM0_EL1
#CHECK-NOV84: mrs x0, MPAM1_EL1
#CHECK-NOV84: mrs x0, MPAM2_EL2
#CHECK-NOV84: mrs x0, MPAM3_EL3
#CHECK-NOV84: mrs x0, MPAM1_EL12
#CHECK-NOV84: mrs x0, MPAMHCR_EL2
#CHECK-NOV84: mrs x0, S3_4_C10_C4_1
#CHECK-NOV84: mrs x0, S3_4_C10_C6_0
#CHECK-NOV84: mrs x0, S3_4_C10_C6_1
@@ -95,5 +100,7 @@
#CHECK-NOV84: mrs x0, S3_4_C10_C6_5
#CHECK-NOV84: mrs x0, S3_4_C10_C6_6
#CHECK-NOV84: mrs x0, S3_4_C10_C6_7
#CHECK-NOV84: mrs x0, S3_0_C10_C4_4
// Available outside MPAM from Armv9.7
#CHECK-NOV84: mrs x0, MPAMIDR_EL1

3
llvm/unittests/TargetParser/TargetParserTest.cpp
View File

@@ -1445,6 +1445,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
AArch64::AEK_SVESM4, AArch64::AEK_CMH,
AArch64::AEK_LSCP, AArch64::AEK_TLBID,
AArch64::AEK_MPAMV2,
};
std::vector<StringRef> Features;
@@ -1559,6 +1560,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+cmh"));
EXPECT_TRUE(llvm::is_contained(Features, "+lscp"));
EXPECT_TRUE(llvm::is_contained(Features, "+tlbid"));
EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2"));
// Assuming we listed every extension above, this should produce the same
// result.
@@ -1728,6 +1730,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"cmh", "nocmh", "+cmh", "-cmh"},
{"lscp", "nolscp", "+lscp", "-lscp"},
{"tlbid", "notlbid", "+tlbid", "-tlbid"},
{"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"},
};
for (unsigned i = 0; i < std::size(ArchExt); i++) {