diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index 8f6185303cd9..b127991f8667 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1561,7 +1561,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S64, {{Sgpr64}, {IntrId, Sgpr64}}) .Div(S64, {{Sgpr64ToVgprDst}, {IntrId, VgprB64}}); - addRulesForIOpcs({amdgcn_bitop3}, Standard) + addRulesForIOpcs({amdgcn_bitop3, amdgcn_fmad_ftz}, Standard) .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}}) .Div(S16, {{Vgpr16}, {IntrId, Vgpr16, Vgpr16, Vgpr16}}) .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}}) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll index a41bf50e4c9d..22b1a4ab4fc7 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll @@ -1,12 +1,41 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "store" --filter-out "load" --filter-out "wait" +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX9-SDAG %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX9-GISEL %s declare half @llvm.amdgcn.fmad.ftz.f16(half %a, half %b, half %c) -; GCN-LABEL: {{^}}mad_f16: -; GCN: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+$}} define amdgpu_kernel void @mad_f16( +; GFX8-LABEL: mad_f16: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v4, s6 +; GFX8: v_mov_b32_e32 v5, s7 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mac_f16_e32 v3, v6, v2 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mac_f16_e32 v3, v1, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s0, v1 +; GFX9-GISEL: v_readfirstlane_b32 s1, v2 +; GFX9-GISEL: v_readfirstlane_b32 s2, v3 +; GFX9-GISEL: v_mov_b32_e32 v1, s1 +; GFX9-GISEL: v_mov_b32_e32 v2, s2 +; GFX9-GISEL: v_mac_f16_e32 v2, s0, v1 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -19,9 +48,34 @@ define amdgpu_kernel void @mad_f16( ret void } -; GCN-LABEL: {{^}}mad_f16_imm_a: -; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+}} +; TODO: GlobalISel should also fold the immediate define amdgpu_kernel void @mad_f16_imm_a( +; GFX8-LABEL: mad_f16_imm_a: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_madmk_f16 v2, v4, 0x4800, v2 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_imm_a: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_madmk_f16 v1, v1, 0x4800, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_imm_a: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s2, v1 +; GFX9-GISEL: v_readfirstlane_b32 s3, v2 +; GFX9-GISEL: v_mov_b32_e32 v1, 0x4800 +; GFX9-GISEL: v_mov_b32_e32 v2, s3 +; GFX9-GISEL: v_mac_f16_e32 v2, s2, v1 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %b, ptr addrspace(1) %c) { @@ -32,9 +86,33 @@ define amdgpu_kernel void @mad_f16_imm_a( ret void } -; GCN-LABEL: {{^}}mad_f16_imm_b: -; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+$}} define amdgpu_kernel void @mad_f16_imm_b( +; GFX8-LABEL: mad_f16_imm_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_madmk_f16 v2, v4, 0x4800, v2 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_imm_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_madmk_f16 v1, v1, 0x4800, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_imm_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s2, v1 +; GFX9-GISEL: v_readfirstlane_b32 s3, v2 +; GFX9-GISEL: v_mov_b32_e32 v1, 0x4800 +; GFX9-GISEL: v_mov_b32_e32 v2, s3 +; GFX9-GISEL: v_mac_f16_e32 v2, s2, v1 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %c) { @@ -45,9 +123,33 @@ define amdgpu_kernel void @mad_f16_imm_b( ret void } -; GCN-LABEL: {{^}}mad_f16_imm_c: -; GCN: v_madak_f16 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4800{{$}} define amdgpu_kernel void @mad_f16_imm_c( +; GFX8-LABEL: mad_f16_imm_c: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_madak_f16 v2, v4, v2, 0x4800 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_imm_c: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_madak_f16 v1, v1, v2, 0x4800 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_imm_c: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s2, v1 +; GFX9-GISEL: v_readfirstlane_b32 s3, v2 +; GFX9-GISEL: v_mov_b32_e32 v1, s3 +; GFX9-GISEL: v_mov_b32_e32 v2, 0x4800 +; GFX9-GISEL: v_mac_f16_e32 v2, s2, v1 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) { @@ -58,10 +160,36 @@ define amdgpu_kernel void @mad_f16_imm_c( ret void } -; GCN-LABEL: {{^}}mad_f16_neg_b: -; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} -; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @mad_f16_neg_b( +; GFX8-LABEL: mad_f16_neg_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v4, s6 +; GFX8: v_mov_b32_e32 v5, s7 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mad_f16 v2, v6, -v2, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_neg_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mad_legacy_f16 v1, v1, -v2, v3 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_neg_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s0, v1 +; GFX9-GISEL: v_readfirstlane_b32 s1, v2 +; GFX9-GISEL: v_readfirstlane_b32 s2, v3 +; GFX9-GISEL: v_max_f16_e64 v1, s1, s1 +; GFX9-GISEL: v_mov_b32_e32 v2, s2 +; GFX9-GISEL: v_mad_legacy_f16 v1, s0, -v1, v2 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -75,10 +203,36 @@ define amdgpu_kernel void @mad_f16_neg_b( ret void } -; GCN-LABEL: {{^}}mad_f16_abs_b: -; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} -; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} define amdgpu_kernel void @mad_f16_abs_b( +; GFX8-LABEL: mad_f16_abs_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v4, s6 +; GFX8: v_mov_b32_e32 v5, s7 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mad_f16 v2, v6, |v2|, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_abs_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mad_legacy_f16 v1, v1, |v2|, v3 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_abs_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s0, v1 +; GFX9-GISEL: v_readfirstlane_b32 s1, v2 +; GFX9-GISEL: v_readfirstlane_b32 s2, v3 +; GFX9-GISEL: v_mov_b32_e32 v1, s0 +; GFX9-GISEL: v_mov_b32_e32 v2, s2 +; GFX9-GISEL: v_mad_legacy_f16 v1, v1, |s1|, v2 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -92,10 +246,36 @@ define amdgpu_kernel void @mad_f16_abs_b( ret void } -; GCN-LABEL: {{^}}mad_f16_neg_abs_b: -; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}} -; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}} define amdgpu_kernel void @mad_f16_neg_abs_b( +; GFX8-LABEL: mad_f16_neg_abs_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s2 +; GFX8: v_mov_b32_e32 v1, s3 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mov_b32_e32 v4, s6 +; GFX8: v_mov_b32_e32 v5, s7 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mad_f16 v2, v6, -|v2|, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f16_neg_abs_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mad_legacy_f16 v1, v1, -|v2|, v3 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f16_neg_abs_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: v_readfirstlane_b32 s0, v1 +; GFX9-GISEL: v_readfirstlane_b32 s1, v2 +; GFX9-GISEL: v_readfirstlane_b32 s2, v3 +; GFX9-GISEL: v_max_f16_e64 v1, |s1|, |s1| +; GFX9-GISEL: v_mov_b32_e32 v2, s2 +; GFX9-GISEL: v_mad_legacy_f16 v1, s0, -v1, v2 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll index 1fdeef7c9125..6d41249facb1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll @@ -1,13 +1,48 @@ -; RUN: llc -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "store" --filter-out "load" --filter-out "wait" +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX6 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX9-SDAG %s +; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GFX9-GISEL %s declare float @llvm.amdgcn.fmad.ftz.f32(float %a, float %b, float %c) -; GCN-LABEL: {{^}}mad_f32: -; GCN: v_ma{{[dc]}}_f32 define amdgpu_kernel void @mad_f32( +; GFX6-LABEL: mad_f32: +; GFX6: ; %bb.0: +; GFX6: s_mov_b32 s11, 0xf000 +; GFX6: s_mov_b32 s10, -1 +; GFX6: s_mov_b32 s8, s0 +; GFX6: s_mov_b32 s9, s1 +; GFX6: v_mov_b32_e32 v0, s6 +; GFX6: v_mov_b32_e32 v1, s4 +; GFX6: v_mac_f32_e32 v0, s2, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s6 +; GFX8: v_mov_b32_e32 v3, s4 +; GFX8: v_mac_f32_e32 v2, s2, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s0 +; GFX9-SDAG: v_mov_b32_e32 v2, s1 +; GFX9-SDAG: v_mac_f32_e32 v1, s2, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, s0 +; GFX9-GISEL: v_mov_b32_e32 v1, s1 +; GFX9-GISEL: v_mac_f32_e32 v1, s2, v0 +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -20,9 +55,43 @@ define amdgpu_kernel void @mad_f32( ret void } -; GCN-LABEL: {{^}}mad_f32_imm_a: -; GCN: v_madmk_f32 {{v[0-9]+}}, {{v[0-9]+}}, 0x41000000, +; TODO: GlobalISel should also fold the immediate define amdgpu_kernel void @mad_f32_imm_a( +; GFX6-LABEL: mad_f32_imm_a: +; GFX6: ; %bb.0: +; GFX6: s_mov_b32 s7, 0xf000 +; GFX6: s_mov_b32 s6, -1 +; GFX6: s_mov_b32 s4, s0 +; GFX6: s_mov_b32 s5, s1 +; GFX6: v_mov_b32_e32 v0, s8 +; GFX6: v_mov_b32_e32 v1, s2 +; GFX6: v_madmk_f32 v0, v1, 0x41000000, v0 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_imm_a: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s2 +; GFX8: v_madmk_f32 v2, v3, 0x41000000, v2 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_imm_a: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s4 +; GFX9-SDAG: v_mov_b32_e32 v2, s5 +; GFX9-SDAG: v_madmk_f32 v1, v2, 0x41000000, v1 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_imm_a: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0x41000000 +; GFX9-GISEL: v_mov_b32_e32 v1, s4 +; GFX9-GISEL: v_mac_f32_e32 v1, s5, v0 +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %b, ptr addrspace(1) %c) { @@ -33,10 +102,42 @@ define amdgpu_kernel void @mad_f32_imm_a( ret void } -; GCN-LABEL: {{^}}mad_f32_imm_b: -; GCN: v_mov_b32_e32 [[KB:v[0-9]+]], 0x41000000 -; GCN: v_mac_f32_e32 {{v[0-9]+}}, {{[s][0-9]+}}, [[KB]] define amdgpu_kernel void @mad_f32_imm_b( +; GFX6-LABEL: mad_f32_imm_b: +; GFX6: ; %bb.0: +; GFX6: v_mov_b32_e32 v1, 0x41000000 +; GFX6: s_mov_b32 s7, 0xf000 +; GFX6: s_mov_b32 s6, -1 +; GFX6: s_mov_b32 s4, s0 +; GFX6: s_mov_b32 s5, s1 +; GFX6: v_mov_b32_e32 v0, s8 +; GFX6: v_mac_f32_e32 v0, s2, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_imm_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v3, 0x41000000 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mac_f32_e32 v2, s2, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_imm_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v2, 0x41000000 +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s4 +; GFX9-SDAG: v_mac_f32_e32 v1, s5, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_imm_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0x41000000 +; GFX9-GISEL: v_mov_b32_e32 v1, s4 +; GFX9-GISEL: v_mac_f32_e32 v1, s5, v0 +; GFX9-GISEL: v_mov_b32_e32 v0, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %c) { @@ -47,13 +148,42 @@ define amdgpu_kernel void @mad_f32_imm_b( ret void } -; GCN-LABEL: {{^}}mad_f32_imm_c: -; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x41000000 -; GCN: s_load_dword [[B:s[0-9]+]] -; GCN: s_load_dword [[A:s[0-9]+]] -; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] -; GCN: v_mac_f32_e32 [[C]], {{s[0-9]+}}, [[VB]]{{$}} define amdgpu_kernel void @mad_f32_imm_c( +; GFX6-LABEL: mad_f32_imm_c: +; GFX6: ; %bb.0: +; GFX6: v_mov_b32_e32 v0, 0x41000000 +; GFX6: s_mov_b32 s7, 0xf000 +; GFX6: s_mov_b32 s6, -1 +; GFX6: s_mov_b32 s4, s0 +; GFX6: s_mov_b32 s5, s1 +; GFX6: v_mov_b32_e32 v1, s8 +; GFX6: v_mac_f32_e32 v0, s2, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_imm_c: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v2, 0x41000000 +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v3, s4 +; GFX8: v_mac_f32_e32 v2, s2, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_imm_c: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v1, 0x41000000 +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v2, s4 +; GFX9-SDAG: v_mac_f32_e32 v1, s5, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_imm_c: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, 0x41000000 +; GFX9-GISEL: v_mov_b32_e32 v1, s4 +; GFX9-GISEL: v_mac_f32_e32 v0, s5, v1 +; GFX9-GISEL: v_mov_b32_e32 v1, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b) { @@ -64,9 +194,42 @@ define amdgpu_kernel void @mad_f32_imm_c( ret void } -; GCN-LABEL: {{^}}mad_f32_neg_b: -; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @mad_f32_neg_b( +; GFX6-LABEL: mad_f32_neg_b: +; GFX6: ; %bb.0: +; GFX6: s_mov_b32 s11, 0xf000 +; GFX6: s_mov_b32 s10, -1 +; GFX6: s_mov_b32 s8, s0 +; GFX6: s_mov_b32 s9, s1 +; GFX6: v_mov_b32_e32 v0, s4 +; GFX6: v_mov_b32_e32 v1, s5 +; GFX6: v_mad_f32 v0, s2, -v0, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_neg_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mad_f32 v2, s2, -v2, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_neg_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s0 +; GFX9-SDAG: v_mov_b32_e32 v2, s1 +; GFX9-SDAG: v_mad_f32 v1, s2, -v1, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_neg_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, s0 +; GFX9-GISEL: v_mov_b32_e32 v1, s1 +; GFX9-GISEL: v_mad_f32 v0, v0, -s2, v1 +; GFX9-GISEL: v_mov_b32_e32 v1, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -80,9 +243,42 @@ define amdgpu_kernel void @mad_f32_neg_b( ret void } -; GCN-LABEL: {{^}}mad_f32_abs_b: -; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} define amdgpu_kernel void @mad_f32_abs_b( +; GFX6-LABEL: mad_f32_abs_b: +; GFX6: ; %bb.0: +; GFX6: s_mov_b32 s11, 0xf000 +; GFX6: s_mov_b32 s10, -1 +; GFX6: s_mov_b32 s8, s0 +; GFX6: s_mov_b32 s9, s1 +; GFX6: v_mov_b32_e32 v0, s4 +; GFX6: v_mov_b32_e32 v1, s5 +; GFX6: v_mad_f32 v0, s2, |v0|, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_abs_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mad_f32 v2, s2, |v2|, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_abs_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s0 +; GFX9-SDAG: v_mov_b32_e32 v2, s1 +; GFX9-SDAG: v_mad_f32 v1, s2, |v1|, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_abs_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, s0 +; GFX9-GISEL: v_mov_b32_e32 v1, s1 +; GFX9-GISEL: v_mad_f32 v0, v0, |s2|, v1 +; GFX9-GISEL: v_mov_b32_e32 v1, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b, @@ -96,9 +292,42 @@ define amdgpu_kernel void @mad_f32_abs_b( ret void } -; GCN-LABEL: {{^}}mad_f32_neg_abs_b: -; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}} define amdgpu_kernel void @mad_f32_neg_abs_b( +; GFX6-LABEL: mad_f32_neg_abs_b: +; GFX6: ; %bb.0: +; GFX6: s_mov_b32 s11, 0xf000 +; GFX6: s_mov_b32 s10, -1 +; GFX6: s_mov_b32 s8, s0 +; GFX6: s_mov_b32 s9, s1 +; GFX6: v_mov_b32_e32 v0, s4 +; GFX6: v_mov_b32_e32 v1, s5 +; GFX6: v_mad_f32 v0, s2, -|v0|, v1 +; GFX6: s_endpgm +; +; GFX8-LABEL: mad_f32_neg_abs_b: +; GFX8: ; %bb.0: +; GFX8: v_mov_b32_e32 v0, s0 +; GFX8: v_mov_b32_e32 v1, s1 +; GFX8: v_mov_b32_e32 v2, s4 +; GFX8: v_mov_b32_e32 v3, s5 +; GFX8: v_mad_f32 v2, s2, -|v2|, v3 +; GFX8: s_endpgm +; +; GFX9-SDAG-LABEL: mad_f32_neg_abs_b: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG: v_mov_b32_e32 v0, 0 +; GFX9-SDAG: v_mov_b32_e32 v1, s0 +; GFX9-SDAG: v_mov_b32_e32 v2, s1 +; GFX9-SDAG: v_mad_f32 v1, s2, -|v1|, v2 +; GFX9-SDAG: s_endpgm +; +; GFX9-GISEL-LABEL: mad_f32_neg_abs_b: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL: v_mov_b32_e32 v0, s0 +; GFX9-GISEL: v_mov_b32_e32 v1, s1 +; GFX9-GISEL: v_mad_f32 v0, v0, -|s2|, v1 +; GFX9-GISEL: v_mov_b32_e32 v1, 0 +; GFX9-GISEL: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, ptr addrspace(1) %b,