[WebAssembly][GlobalISel] CallLowering lowerFormalArguments (#180263)
Implements `WebAssemblyCallLowering::lowerFormalArguments` Split from #157161
This commit is contained in:
Demetrius Kanios
@@ -14,11 +14,17 @@
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#include "WebAssemblyCallLowering.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "Utils/WasmAddressSpaces.h"
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#include "WebAssemblyISelLowering.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblyRegisterInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterBankInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Value.h"
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@@ -27,6 +33,21 @@
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using namespace llvm;
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// Test whether the given calling convention is supported.
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static bool callingConvSupported(CallingConv::ID CallConv) {
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// We currently support the language-independent target-independent
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// conventions. We don't yet have a way to annotate calls with properties like
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// "cold", and we don't have any call-clobbered registers, so these are mostly
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// all handled the same.
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return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
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CallConv == CallingConv::Cold ||
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CallConv == CallingConv::PreserveMost ||
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CallConv == CallingConv::PreserveAll ||
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CallConv == CallingConv::CXX_FAST_TLS ||
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CallConv == CallingConv::WASM_EmscriptenInvoke ||
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CallConv == CallingConv::Swift;
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}
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WebAssemblyCallLowering::WebAssemblyCallLowering(
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const WebAssemblyTargetLowering &TLI)
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: CallLowering(&TLI) {}
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@@ -50,13 +71,222 @@ bool WebAssemblyCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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return false;
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}
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static unsigned getWASMArgumentOpcode(MVT ArgType) {
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switch (ArgType.SimpleTy) {
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case MVT::i32:
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return WebAssembly::ARGUMENT_i32;
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case MVT::i64:
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return WebAssembly::ARGUMENT_i64;
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case MVT::f32:
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return WebAssembly::ARGUMENT_f32;
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case MVT::f64:
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return WebAssembly::ARGUMENT_f64;
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case MVT::funcref:
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return WebAssembly::ARGUMENT_funcref;
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case MVT::externref:
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return WebAssembly::ARGUMENT_externref;
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case MVT::exnref:
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return WebAssembly::ARGUMENT_exnref;
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case MVT::v16i8:
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return WebAssembly::ARGUMENT_v16i8;
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case MVT::v8i16:
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return WebAssembly::ARGUMENT_v8i16;
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case MVT::v4i32:
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return WebAssembly::ARGUMENT_v4i32;
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case MVT::v2i64:
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return WebAssembly::ARGUMENT_v2i64;
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case MVT::v8f16:
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return WebAssembly::ARGUMENT_v8f16;
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case MVT::v4f32:
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return WebAssembly::ARGUMENT_v4f32;
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case MVT::v2f64:
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return WebAssembly::ARGUMENT_v2f64;
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default:
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break;
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}
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llvm_unreachable("Found unexpected type for WASM argument");
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}
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static LLT getLLTForWasmMVT(MVT Ty, const DataLayout &DL) {
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if (Ty == MVT::externref) {
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return LLT::pointer(
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WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_EXTERNREF,
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DL.getPointerSizeInBits(
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WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_EXTERNREF));
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}
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if (Ty == MVT::funcref) {
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return LLT::pointer(
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WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_FUNCREF,
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DL.getPointerSizeInBits(
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WebAssembly::WasmAddressSpace::WASM_ADDRESS_SPACE_FUNCREF));
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}
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return llvm::getLLTForMVT(Ty);
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}
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bool WebAssemblyCallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
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if (VRegs.empty())
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return true; // allow only empty signatures for now
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MachineFunction &MF = MIRBuilder.getMF();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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WebAssemblyFunctionInfo *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
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const DataLayout &DL = F.getDataLayout();
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const WebAssemblyTargetLowering &TLI = *getTLI<WebAssemblyTargetLowering>();
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const WebAssemblySubtarget &Subtarget =
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MF.getSubtarget<WebAssemblySubtarget>();
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const WebAssemblyRegisterInfo &TRI = *Subtarget.getRegisterInfo();
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const WebAssemblyInstrInfo &TII = *Subtarget.getInstrInfo();
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const RegisterBankInfo &RBI = *Subtarget.getRegBankInfo();
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return false;
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LLVMContext &Ctx = MIRBuilder.getContext();
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const CallingConv::ID CallConv = F.getCallingConv();
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if (!callingConvSupported(CallConv)) {
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return false;
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}
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MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
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MF.front().addLiveIn(WebAssembly::ARGUMENTS);
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SmallVector<ArgInfo, 8> SplitArgs;
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if (!FLI.CanLowerReturn) {
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insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
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}
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unsigned ArgIdx = 0;
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bool HasSwiftErrorArg = false;
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bool HasSwiftSelfArg = false;
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for (const Argument &Arg : F.args()) {
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ArgInfo OrigArg{VRegs[ArgIdx], Arg.getType(), ArgIdx};
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setArgFlags(OrigArg, ArgIdx + AttributeList::FirstArgIndex, DL, F);
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HasSwiftSelfArg |= Arg.hasSwiftSelfAttr();
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HasSwiftErrorArg |= Arg.hasSwiftErrorAttr();
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if (Arg.hasInAllocaAttr()) {
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return false;
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}
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if (Arg.hasNestAttr()) {
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return false;
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}
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splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
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++ArgIdx;
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}
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unsigned FinalArgIdx = 0;
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for (ArgInfo &Arg : SplitArgs) {
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const EVT OrigVT = TLI.getValueType(DL, Arg.Ty);
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const MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CallConv, OrigVT);
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const LLT OrigLLT =
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getLLTForType(*OrigVT.getTypeForEVT(F.getContext()), DL);
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const LLT NewLLT = getLLTForWasmMVT(NewVT, DL);
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// If we need to split the type over multiple regs, check it's a scenario
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// we currently support.
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const unsigned NumParts =
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TLI.getNumRegistersForCallingConv(Ctx, CallConv, OrigVT);
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const ISD::ArgFlagsTy OrigFlags = Arg.Flags[0];
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Arg.Flags.clear();
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for (unsigned Part = 0; Part < NumParts; ++Part) {
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ISD::ArgFlagsTy Flags = OrigFlags;
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if (Part == 0) {
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Flags.setSplit();
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} else {
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Flags.setOrigAlign(Align(1));
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if (Part == NumParts - 1)
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Flags.setSplitEnd();
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}
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Arg.Flags.push_back(Flags);
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}
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Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end());
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if (NumParts != 1 || OrigLLT != NewLLT) {
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// If we can't directly assign the register, we need one or more
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// intermediate values.
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Arg.Regs.resize(NumParts);
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// For each split register, create and assign a vreg that will store
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// the incoming component of the larger value. These will later be
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// merged to form the final vreg.
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for (unsigned Part = 0; Part < NumParts; ++Part) {
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Arg.Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
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}
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}
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for (unsigned Part = 0; Part < NumParts; ++Part) {
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MachineInstrBuilder ArgInst =
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MIRBuilder.buildInstr(getWASMArgumentOpcode(NewVT))
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.addDef(Arg.Regs[Part])
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.addImm(FinalArgIdx);
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constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *ArgInst,
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ArgInst->getDesc(), ArgInst->getOperand(0), 0);
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MFI->addParam(NewVT);
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++FinalArgIdx;
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}
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if (OrigVT != NewVT) {
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buildCopyFromRegs(MIRBuilder, Arg.OrigRegs, Arg.Regs, OrigLLT, NewLLT,
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Arg.Flags[0]);
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}
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}
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// For swiftcc, emit additional swiftself and swifterror arguments
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// if there aren't. These additional arguments are also added for callee
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// signature They are necessary to match callee and caller signature for
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// indirect call.
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if (CallConv == CallingConv::Swift) {
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const MVT PtrVT = TLI.getPointerTy(DL);
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if (!HasSwiftSelfArg) {
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MFI->addParam(PtrVT);
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}
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if (!HasSwiftErrorArg) {
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MFI->addParam(PtrVT);
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}
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}
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// Varargs are copied into a buffer allocated by the caller, and a pointer to
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// the buffer is passed as an argument.
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if (F.isVarArg()) {
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const MVT PtrVT = TLI.getPointerTy(DL, 0);
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const LLT PtrLLT = LLT::pointer(0, DL.getPointerSizeInBits(0));
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Register VarargVreg = MF.getRegInfo().createGenericVirtualRegister(PtrLLT);
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MFI->setVarargBufferVreg(VarargVreg);
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MachineInstrBuilder ArgInst =
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MIRBuilder.buildInstr(getWASMArgumentOpcode(PtrVT))
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.addDef(VarargVreg)
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.addImm(FinalArgIdx);
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constrainOperandRegClass(MF, TRI, MRI, TII, RBI, *ArgInst,
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ArgInst->getDesc(), ArgInst->getOperand(0), 0);
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MFI->addParam(PtrVT);
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++FinalArgIdx;
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}
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// Record the number and types of arguments and results.
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SmallVector<MVT, 4> Params;
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SmallVector<MVT, 4> Results;
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computeSignatureVTs(MF.getFunction().getFunctionType(), &MF.getFunction(),
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MF.getFunction(), MF.getTarget(), Params, Results);
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for (MVT VT : Results)
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MFI->addResult(VT);
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// TODO: Use signatures in WebAssemblyMachineFunctionInfo too and unify
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// the param logic here with ComputeSignatureVTs
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assert(MFI->getParams().size() == Params.size() &&
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std::equal(MFI->getParams().begin(), MFI->getParams().end(),
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Params.begin()));
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return true;
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}
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bool WebAssemblyCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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@@ -0,0 +1,171 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=wasm32 -mattr=-simd128 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=NO-SIMD
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; RUN: llc -mtriple=wasm32 -mattr=+simd128,-fp16 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SIMD,SIMD-NO-F16
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; RUN: llc -mtriple=wasm32 -mattr=+simd128,+fp16 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SIMD,SIMD-F16
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define void @test_v16i8_arg(<16 x i8> %arg) {
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; NO-SIMD-LABEL: name: test_v16i8_arg
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; NO-SIMD: bb.1 (%ir-block.0):
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; NO-SIMD-NEXT: liveins: $arguments
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; NO-SIMD-NEXT: {{ $}}
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; NO-SIMD-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_4:%[0-9]+]]:i32(s32) = ARGUMENT_i32 4, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_5:%[0-9]+]]:i32(s32) = ARGUMENT_i32 5, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_6:%[0-9]+]]:i32(s32) = ARGUMENT_i32 6, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_7:%[0-9]+]]:i32(s32) = ARGUMENT_i32 7, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_8:%[0-9]+]]:i32(s32) = ARGUMENT_i32 8, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_9:%[0-9]+]]:i32(s32) = ARGUMENT_i32 9, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_10:%[0-9]+]]:i32(s32) = ARGUMENT_i32 10, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_11:%[0-9]+]]:i32(s32) = ARGUMENT_i32 11, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_12:%[0-9]+]]:i32(s32) = ARGUMENT_i32 12, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_13:%[0-9]+]]:i32(s32) = ARGUMENT_i32 13, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_14:%[0-9]+]]:i32(s32) = ARGUMENT_i32 14, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_15:%[0-9]+]]:i32(s32) = ARGUMENT_i32 15, implicit $arguments
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; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](s32), [[ARGUMENT_i32_1]](s32), [[ARGUMENT_i32_2]](s32), [[ARGUMENT_i32_3]](s32), [[ARGUMENT_i32_4]](s32), [[ARGUMENT_i32_5]](s32), [[ARGUMENT_i32_6]](s32), [[ARGUMENT_i32_7]](s32), [[ARGUMENT_i32_8]](s32), [[ARGUMENT_i32_9]](s32), [[ARGUMENT_i32_10]](s32), [[ARGUMENT_i32_11]](s32), [[ARGUMENT_i32_12]](s32), [[ARGUMENT_i32_13]](s32), [[ARGUMENT_i32_14]](s32), [[ARGUMENT_i32_15]](s32)
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; NO-SIMD-NEXT: [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR]](<16 x s32>)
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;
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; SIMD-LABEL: name: test_v16i8_arg
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; SIMD: bb.1 (%ir-block.0):
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; SIMD-NEXT: liveins: $arguments
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; SIMD-NEXT: {{ $}}
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; SIMD-NEXT: [[ARGUMENT_v16i8_:%[0-9]+]]:v128(<16 x s8>) = ARGUMENT_v16i8 0, implicit $arguments
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ret void
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}
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define void @test_v8i16_arg(<8 x i16> %arg) {
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; NO-SIMD-LABEL: name: test_v8i16_arg
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; NO-SIMD: bb.1 (%ir-block.0):
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; NO-SIMD-NEXT: liveins: $arguments
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; NO-SIMD-NEXT: {{ $}}
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; NO-SIMD-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_4:%[0-9]+]]:i32(s32) = ARGUMENT_i32 4, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_5:%[0-9]+]]:i32(s32) = ARGUMENT_i32 5, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_6:%[0-9]+]]:i32(s32) = ARGUMENT_i32 6, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_7:%[0-9]+]]:i32(s32) = ARGUMENT_i32 7, implicit $arguments
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; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](s32), [[ARGUMENT_i32_1]](s32), [[ARGUMENT_i32_2]](s32), [[ARGUMENT_i32_3]](s32), [[ARGUMENT_i32_4]](s32), [[ARGUMENT_i32_5]](s32), [[ARGUMENT_i32_6]](s32), [[ARGUMENT_i32_7]](s32)
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; NO-SIMD-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
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;
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; SIMD-LABEL: name: test_v8i16_arg
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; SIMD: bb.1 (%ir-block.0):
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; SIMD-NEXT: liveins: $arguments
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; SIMD-NEXT: {{ $}}
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; SIMD-NEXT: [[ARGUMENT_v8i16_:%[0-9]+]]:v128(<8 x s16>) = ARGUMENT_v8i16 0, implicit $arguments
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ret void
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}
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define void @test_v4i32_arg(<4 x i32> %arg) {
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; NO-SIMD-LABEL: name: test_v4i32_arg
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; NO-SIMD: bb.1 (%ir-block.0):
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; NO-SIMD-NEXT: liveins: $arguments
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; NO-SIMD-NEXT: {{ $}}
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; NO-SIMD-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
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; NO-SIMD-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
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; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](s32), [[ARGUMENT_i32_1]](s32), [[ARGUMENT_i32_2]](s32), [[ARGUMENT_i32_3]](s32)
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;
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; SIMD-LABEL: name: test_v4i32_arg
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; SIMD: bb.1 (%ir-block.0):
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; SIMD-NEXT: liveins: $arguments
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; SIMD-NEXT: {{ $}}
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; SIMD-NEXT: [[ARGUMENT_v4i32_:%[0-9]+]]:v128(<4 x s32>) = ARGUMENT_v4i32 0, implicit $arguments
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ret void
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}
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define void @test_v2i64_arg(<2 x i64> %arg) {
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; NO-SIMD-LABEL: name: test_v2i64_arg
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; NO-SIMD: bb.1 (%ir-block.0):
|
||||
; NO-SIMD-NEXT: liveins: $arguments
|
||||
; NO-SIMD-NEXT: {{ $}}
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ARGUMENT_i64_]](s64), [[ARGUMENT_i64_1]](s64)
|
||||
;
|
||||
; SIMD-LABEL: name: test_v2i64_arg
|
||||
; SIMD: bb.1 (%ir-block.0):
|
||||
; SIMD-NEXT: liveins: $arguments
|
||||
; SIMD-NEXT: {{ $}}
|
||||
; SIMD-NEXT: [[ARGUMENT_v2i64_:%[0-9]+]]:v128(<2 x s64>) = ARGUMENT_v2i64 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v8f16_arg(<8 x half> %arg) {
|
||||
; NO-SIMD-LABEL: name: test_v8f16_arg
|
||||
; NO-SIMD: bb.1 (%ir-block.0):
|
||||
; NO-SIMD-NEXT: liveins: $arguments
|
||||
; NO-SIMD-NEXT: {{ $}}
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_4:%[0-9]+]]:i32(s32) = ARGUMENT_i32 4, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_5:%[0-9]+]]:i32(s32) = ARGUMENT_i32 5, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_6:%[0-9]+]]:i32(s32) = ARGUMENT_i32 6, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_i32_7:%[0-9]+]]:i32(s32) = ARGUMENT_i32 7, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](s32), [[ARGUMENT_i32_1]](s32), [[ARGUMENT_i32_2]](s32), [[ARGUMENT_i32_3]](s32), [[ARGUMENT_i32_4]](s32), [[ARGUMENT_i32_5]](s32), [[ARGUMENT_i32_6]](s32), [[ARGUMENT_i32_7]](s32)
|
||||
; NO-SIMD-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
|
||||
;
|
||||
; SIMD-NO-F16-LABEL: name: test_v8f16_arg
|
||||
; SIMD-NO-F16: bb.1 (%ir-block.0):
|
||||
; SIMD-NO-F16-NEXT: liveins: $arguments
|
||||
; SIMD-NO-F16-NEXT: {{ $}}
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_4:%[0-9]+]]:i32(s32) = ARGUMENT_i32 4, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_5:%[0-9]+]]:i32(s32) = ARGUMENT_i32 5, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_6:%[0-9]+]]:i32(s32) = ARGUMENT_i32 6, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[ARGUMENT_i32_7:%[0-9]+]]:i32(s32) = ARGUMENT_i32 7, implicit $arguments
|
||||
; SIMD-NO-F16-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ARGUMENT_i32_]](s32), [[ARGUMENT_i32_1]](s32), [[ARGUMENT_i32_2]](s32), [[ARGUMENT_i32_3]](s32), [[ARGUMENT_i32_4]](s32), [[ARGUMENT_i32_5]](s32), [[ARGUMENT_i32_6]](s32), [[ARGUMENT_i32_7]](s32)
|
||||
; SIMD-NO-F16-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s16>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
|
||||
;
|
||||
; SIMD-F16-LABEL: name: test_v8f16_arg
|
||||
; SIMD-F16: bb.1 (%ir-block.0):
|
||||
; SIMD-F16-NEXT: liveins: $arguments
|
||||
; SIMD-F16-NEXT: {{ $}}
|
||||
; SIMD-F16-NEXT: [[ARGUMENT_v8f16_:%[0-9]+]]:v128(<8 x s16>) = ARGUMENT_v8f16 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v4f32_arg(<4 x float> %arg) {
|
||||
; NO-SIMD-LABEL: name: test_v4f32_arg
|
||||
; NO-SIMD: bb.1 (%ir-block.0):
|
||||
; NO-SIMD-NEXT: liveins: $arguments
|
||||
; NO-SIMD-NEXT: {{ $}}
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 0, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f32_1:%[0-9]+]]:f32(s32) = ARGUMENT_f32 1, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f32_2:%[0-9]+]]:f32(s32) = ARGUMENT_f32 2, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f32_3:%[0-9]+]]:f32(s32) = ARGUMENT_f32 3, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ARGUMENT_f32_]](s32), [[ARGUMENT_f32_1]](s32), [[ARGUMENT_f32_2]](s32), [[ARGUMENT_f32_3]](s32)
|
||||
;
|
||||
; SIMD-LABEL: name: test_v4f32_arg
|
||||
; SIMD: bb.1 (%ir-block.0):
|
||||
; SIMD-NEXT: liveins: $arguments
|
||||
; SIMD-NEXT: {{ $}}
|
||||
; SIMD-NEXT: [[ARGUMENT_v4f32_:%[0-9]+]]:v128(<4 x s32>) = ARGUMENT_v4f32 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2f64_arg(<2 x double> %arg) {
|
||||
; NO-SIMD-LABEL: name: test_v2f64_arg
|
||||
; NO-SIMD: bb.1 (%ir-block.0):
|
||||
; NO-SIMD-NEXT: liveins: $arguments
|
||||
; NO-SIMD-NEXT: {{ $}}
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f64_:%[0-9]+]]:f64(s64) = ARGUMENT_f64 0, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[ARGUMENT_f64_1:%[0-9]+]]:f64(s64) = ARGUMENT_f64 1, implicit $arguments
|
||||
; NO-SIMD-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ARGUMENT_f64_]](s64), [[ARGUMENT_f64_1]](s64)
|
||||
;
|
||||
; SIMD-LABEL: name: test_v2f64_arg
|
||||
; SIMD: bb.1 (%ir-block.0):
|
||||
; SIMD-NEXT: liveins: $arguments
|
||||
; SIMD-NEXT: {{ $}}
|
||||
; SIMD-NEXT: [[ARGUMENT_v2f64_:%[0-9]+]]:v128(<2 x s64>) = ARGUMENT_v2f64 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
@@ -0,0 +1,73 @@
|
||||
; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM32
|
||||
; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM64
|
||||
|
||||
define swiftcc void @test_implicit_self_and_error(float %arg) {
|
||||
; CHECK-LABEL: name: test_implicit_self_and_error
|
||||
|
||||
; CHECK: machineFunctionInfo:
|
||||
; WASM32-NEXT: params: [ f32, i32, i32 ]
|
||||
; WASM64-NEXT: params: [ f32, i64, i64 ]
|
||||
; CHECK-NEXT: results: [ ]
|
||||
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define swiftcc void @test_explicit_self_and_implicit_error(ptr swiftself %self, float %arg) {
|
||||
; CHECK-LABEL: name: test_explicit_self_and_implicit_error
|
||||
|
||||
|
||||
; CHECK: machineFunctionInfo:
|
||||
; WASM32-NEXT: params: [ i32, f32, i32 ]
|
||||
; WASM64-NEXT: params: [ i64, f32, i64 ]
|
||||
; CHECK-NEXT: results: [ ]
|
||||
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 1, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define swiftcc void @test_implicit_self_and_explicit_error(ptr swifterror %error, float %arg) {
|
||||
; CHECK-LABEL: name: test_implicit_self_and_explicit_error
|
||||
|
||||
|
||||
; CHECK: machineFunctionInfo:
|
||||
; WASM32-NEXT: params: [ i32, f32, i32 ]
|
||||
; WASM64-NEXT: params: [ i64, f32, i64 ]
|
||||
; CHECK-NEXT: results: [ ]
|
||||
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 1, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define swiftcc void @test_explicit_self_and_error(ptr swiftself %self, ptr swifterror %error, float %arg) {
|
||||
; CHECK-LABEL: name: test_explicit_self_and_error
|
||||
|
||||
|
||||
; CHECK: machineFunctionInfo:
|
||||
; WASM32-NEXT: params: [ i32, i32, f32 ]
|
||||
; WASM64-NEXT: params: [ i64, i64, f32 ]
|
||||
; CHECK-NEXT: results: [ ]
|
||||
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(p0) = ARGUMENT_i32 1, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(p0) = ARGUMENT_i64 1, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 2, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
209
llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
Normal file
209
llvm/test/CodeGen/WebAssembly/GlobalISel/irtranslator/args.ll
Normal file
@@ -0,0 +1,209 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
|
||||
; RUN: llc -mtriple=wasm32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM32
|
||||
; RUN: llc -mtriple=wasm64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,WASM64
|
||||
|
||||
define void @test_i8_arg(i8 %arg) {
|
||||
; CHECK-LABEL: name: test_i8_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_i8_zeroext_arg(i8 zeroext %arg) {
|
||||
; CHECK-LABEL: name: test_i8_zeroext_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ARGUMENT_i32_]], 8
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_i8_signext_arg(i8 signext %arg) {
|
||||
; CHECK-LABEL: name: test_i8_signext_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[ARGUMENT_i32_]], 8
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_i16_arg(i16 %arg) {
|
||||
; CHECK-LABEL: name: test_i16_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @test_i32_arg(i32 %arg) {
|
||||
; CHECK-LABEL: name: test_i32_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @test_i64_arg(i64 %arg) {
|
||||
; CHECK-LABEL: name: test_i64_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_ptr_arg(ptr %arg) {
|
||||
; WASM32-LABEL: name: test_ptr_arg
|
||||
; WASM32: bb.1 (%ir-block.0):
|
||||
; WASM32-NEXT: liveins: $arguments
|
||||
; WASM32-NEXT: {{ $}}
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
|
||||
;
|
||||
; WASM64-LABEL: name: test_ptr_arg
|
||||
; WASM64: bb.1 (%ir-block.0):
|
||||
; WASM64-NEXT: liveins: $arguments
|
||||
; WASM64-NEXT: {{ $}}
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_i128_arg(i128 %arg) {
|
||||
; CHECK-LABEL: name: test_i128_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
|
||||
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ARGUMENT_i64_]](s64), [[ARGUMENT_i64_1]](s64)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_f16_arg(half %arg) {
|
||||
; CHECK-LABEL: name: test_f16_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @test_f32_arg(float %arg) {
|
||||
; CHECK-LABEL: name: test_f32_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @test_f64_arg(double %arg) {
|
||||
; CHECK-LABEL: name: test_f64_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_f64_:%[0-9]+]]:f64(s64) = ARGUMENT_f64 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_f128_arg(fp128 %arg) {
|
||||
; CHECK-LABEL: name: test_f128_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 0, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_1:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
|
||||
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[ARGUMENT_i64_]](s64), [[ARGUMENT_i64_1]](s64)
|
||||
ret void
|
||||
}
|
||||
|
||||
%externref = type ptr addrspace(10)
|
||||
define void @test_externref_arg(%externref %arg) {
|
||||
; CHECK-LABEL: name: test_externref_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_externref:%[0-9]+]]:externref(p10) = ARGUMENT_externref 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
%funcref = type ptr addrspace(20)
|
||||
define void @test_funcref_arg(%funcref %arg) {
|
||||
; CHECK-LABEL: name: test_funcref_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_funcref:%[0-9]+]]:funcref(p20) = ARGUMENT_funcref 0, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_multiple_args(ptr %arg1, float %arg2, i1 %arg3) {
|
||||
; WASM32-LABEL: name: test_multiple_args
|
||||
; WASM32: bb.1 (%ir-block.0):
|
||||
; WASM32-NEXT: liveins: $arguments
|
||||
; WASM32-NEXT: {{ $}}
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(p0) = ARGUMENT_i32 0, implicit $arguments
|
||||
; WASM32-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 1, implicit $arguments
|
||||
; WASM32-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; WASM32-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ARGUMENT_i32_1]](s32)
|
||||
;
|
||||
; WASM64-LABEL: name: test_multiple_args
|
||||
; WASM64: bb.1 (%ir-block.0):
|
||||
; WASM64-NEXT: liveins: $arguments
|
||||
; WASM64-NEXT: {{ $}}
|
||||
; WASM64-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(p0) = ARGUMENT_i64 0, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 1, implicit $arguments
|
||||
; WASM64-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; WASM64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_array_arg([5 x i16] %arg) {
|
||||
; CHECK-LABEL: name: test_array_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 1, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_1]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_2]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_3:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_3]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_4:%[0-9]+]]:i32(s32) = ARGUMENT_i32 4, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_4]](s32)
|
||||
ret void
|
||||
}
|
||||
|
||||
%StructTy = type { i8, i64, i16, i1, float }
|
||||
|
||||
define void @test_struct_arg(%StructTy %arg) {
|
||||
; CHECK-LABEL: name: test_struct_arg
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK-NEXT: liveins: $arguments
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_:%[0-9]+]]:i32(s32) = ARGUMENT_i32 0, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ARGUMENT_i32_]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i64_:%[0-9]+]]:i64(s64) = ARGUMENT_i64 1, implicit $arguments
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_1:%[0-9]+]]:i32(s32) = ARGUMENT_i32 2, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ARGUMENT_i32_1]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_i32_2:%[0-9]+]]:i32(s32) = ARGUMENT_i32 3, implicit $arguments
|
||||
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ARGUMENT_i32_2]](s32)
|
||||
; CHECK-NEXT: [[ARGUMENT_f32_:%[0-9]+]]:f32(s32) = ARGUMENT_f32 4, implicit $arguments
|
||||
ret void
|
||||
}
|
||||
Reference in New Issue
Block a user